STRUCT CLK_ALPHA_PLL_POSTDIV(9)

✨ NAME ✨

struct clk_alpha_pll_postdiv — the phase locked loop (PLL) post-divider, bestie 💅

okay so real talk, this is the page for struct clk_a..._pll_postdiv(9) straight out of the Kernel API Manual, and honestly? it's giving "small struct, big job" energy 👑

🌸 SYNOPSIS 🌸

here's the whole thing, no cap, exactly as it lives:

struct clk_alpha_pll_postdiv {
    u32 offset;
    u8 width;
    const u8 *regs;
    struct clk_regmap clkr;
    int post_div_shift;
    const struct clk_div_table *post_div_table;
    size_t num_post_div;
};

🦋 MEMBERS 🦋

okay lemme walk you through every single field because we do NOT skip ✨

• offset — the base address of the registers. like, where the whole party lives 🏠
• width — how wide the post-divider is. that's it, that's the tweet.
• regs — the alpha pll register map (see clk_alpha_pll_regs). the little map of where everything is 🗺️
• clkr — the regmap clock handle. your main character handle fr fr 💖
• post_div_shift — the shift that differentiates between an odd & even post-divider. yes, odd AND even, she contains multitudes 🫶
• post_div_table — the table with the PLL odd and even post-divider settings. all the settings, organized, iconic 🎀
• num_post_div — the number of PLL post-divider settings. gotta know how many you've got, periodt 🔥

🌈 SEE ALSO 🌈

• Kernel file ./drivers/clk/qcom/clk-alpha-pll.h
• struct clk_alpha_pll(9) — go read her too, she's the sibling 💜

and that's the whole page, bestie, you ATE that 🍓

this was the struct clk_a..._pll_postdiv(9) page from the Kernel API Manual, coming at you from ./drivers/clk/qcom, dated October 2026 — take care of her, she's iconic 👑✨💅