STRUCT CDNS_PCIE_EP(9)

💖 NAME 💖

okay so this is the struct cdns_pcie_ep(9) page from the Kernel API Manual, and it’s literally the private data for this PCIe endpoint controller driver. bestie, it’s the struct’s main character arc: all the endpoint controller’s private little details live here. 💅✨

✨ SYNOPSIS ✨

no cap, here’s the exact struct shape — do not lose a single field, okay?

struct cdns_pcie_ep {
    struct cdns_pcie        pcie;
    u32 max_regions;
    unsigned long           ob_region_map;
    phys_addr_t *ob_addr;
    phys_addr_t irq_phys_addr;
    void __iomem            *irq_cpu_addr;
    u64 irq_pci_addr;
    u8 irq_pci_fn;
    u8 irq_pending;
    spinlock_t lock;
    struct cdns_pcie_epf    *epf;
    unsigned int            quirk_detect_quiet_flag:1;
    unsigned int            quirk_disable_flr:1;
 };

🫶 MEMBERS 🫶

• pcie — the Cadence PCIe controller. iconic. that’s the controller vibe right there. 🎀
• max_regions — maximum number of regions supported by hardware. yes, hardware says how many regions it can handle, and this is the limit. 💅
• ob_region_map — bitmask of mapped outbound regions. lowkey a little map of which outbound regions are mapped. ✨
• ob_addr — base addresses in the AXI bus where the outbound regions start. this is where they begin on the AXI bus, periodt. 🦋
• irq_phys_addr — base address on the AXI bus where the MSI/INTX IRQ dedicated outbound regions is mapped. yep, that exact thing. 🌸
• irq_cpu_addr — base address in the CPU space where a write access triggers the sending of a memory write (MSI) / normal message (INTX IRQ) TLP through the PCIe bus. the whole trigger-a-TLP situation. 🔥
• irq_pci_addr — used to save the current mapping of the MSI/INTX IRQ dedicated outbound region. saving the current mapping, not me forgetting it. 🙈
• irq_pci_fn — the latest PCI function that has updated the mapping of the MSI/INTX IRQ dedicated outbound region. the latest updater, iykyk. 👑
• irq_pending — bitmask of asserted INTX IRQs. bitmask, asserted, INTX IRQs — all of that. ⭐
• lock — spin lock to disable interrupts while modifying PCIe controller registers fields (RMW) accessible by both remote RC and EP to minimize time between read and write. dramatic? maybe. important? absolutely. 🔒
• epf — structure to hold info about endpoint function. it’s giving endpoint-function info holder energy. 🧚
• quirk_detect_quiet_flag — LTSSM Detect Quiet min delay set as quirk. quirk flag, slay. 💜
• quirk_disable_flr — Disable FLR (Function Level Reset) quirk flag. that’s the FLR-disable quirk flag, bestie. 🌈

🔍 SEE ALSO 🔍

want more lore? go peek at the kernel file ./drivers/pci/controller/cadence/pcie-cadence.h and also check out struct cdns_plat_pcie_of_data(9), struct cdns_pcie(9), struct cdns_pcie_rc(9), and struct cdns_pcie_epf(9). the whole cadence crew fr fr. 🫶

mwah 💋 cute little sign-off: this page’s source/version situation is ./drivers/pci/controller/cadence, dated October 2026, and the manual page is struct cdns_pcie_ep(9). bye bestie, go read the struct! 🎀✨