STRUCT CDNS_PCIE(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

✨ struct cdns_pcie β€” the whole vibe ✨

okay so bestie, let me introduce you to struct cdns_pcie πŸ’… this is literally the private data situation for the Cadence PCIe controller drivers. it's giving "backstage pass to the PCIe show," no cap. πŸŽ€


🌸 SYNOPSIS 🌸

struct cdns_pcie {
    void __iomem                         *reg_base;
    struct resource                      *mem_res;
    struct resource                      *msg_res;
    struct device                        *dev;
    bool is_rc;
    bool is_hpa;
    int phy_count;
    struct phy                           **phy;
    struct device_link                   **link;
    const struct cdns_pcie_ops          *ops;
    const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
    int max_link_speed;
    struct dentry                        *debug_dir;
 };

πŸ‘‘ Members (the whole cast, and they all ate) πŸ‘‘

  • reg_base β€” the IO mapped register base. like, the home address of all the register energy 🏠✨
  • mem_res β€” start/end offsets in the physical system memory, specifically for mapping PCI accesses. it's the map, bestie πŸ—ΊοΈ
  • msg_res β€” the region for send message to map PCI accesses. dedicated message lane, periodt πŸ’Œ
  • dev β€” the PCIe controller itself. main character energy fr fr 🌟
  • is_rc β€” tells you whether the PCIe controller mode is Root Complex or Endpoint. literally the "which one am I" flag πŸ™ˆ
  • is_hpa β€” indicates if the architecture is HPA. yes ma'am, noted 🫢
  • phy_count β€” number of supported PHY devices. the headcount, iykyk πŸ”’
  • phy β€” list of pointers to specific PHY control blocks. a whole friend group of pointers πŸ’–
  • link β€” list of pointers to corresponding device link representations. the connections, the lore πŸ”—
  • ops β€” platform-specific ops to control various inputs from the Cadence PCIe wrapper. this is the customizable slay layer πŸŽ›οΈ
  • cdns_pcie_reg_offsets β€” register bank offsets for different SoC. different SoCs, different offsets, same iconic energy 🌈
  • max_link_speed β€” maximum supported link speed. the speed limit, and it's highkey important πŸŽοΈπŸ’¨
  • debug_dir β€” the debugfs node. where the debugging besties hang out πŸ›πŸ”

πŸ¦‹ SEE ALSO πŸ¦‹

kernel file ./drivers/pci/controller/cadence/pcie-cadence.h struct cdns_plat_pcie_of_data(9), struct cdns_pcie_rc(9), struct cdns_pcie_epf(9), struct cdns_pcie_ep(9) β€” go read these too, bestie, they're all part of the family 🫢✨


and that's the whole page, no notes πŸ’… this little icon lives in ./drivers/pci/controller/cadence, dated October 2026, and it's brought to you by the struct cdns_pcie(9) manual. slay and goodbye πŸŽ€πŸŒŸ

πŸ“¦ where this page comes from