STRUCT CCU_PLL_RATE_TBL(9)

🎀 struct ccu_pll_rate_tbl(9) 🎀

okay so bestie, we're in the Kernel API Manual and this page is literally about a struct. a struct!! and she's the entire vibe of rate↔register mapping. let's go 💅

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✨ NAME ✨

struct ccu_pll_rate_tbl — the structure that maps between PLL rate and register configuration. that's it, that's the whole job, and she does it flawlessly 💖

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✨ SYNOPSIS ✨

struct ccu_pll_rate_tbl {
    unsigned long rate;
    u32 swcr1;
    u32 swcr2;
    u32 swcr3;
 };

like, four fields. clean. iconic. no notes 👑

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🌸 Members 🌸

• rate — the PLL rate 🫶
• swcr1 — value of register PLLx_SW1_CTRL
• swcr2 — value of register PLLAx_SW2_CTRL
• swcr3 — value of register PLLx_SW3_CTRL (yes it says lowercase value up there, keeping it real, we don't edit history 💀)

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✨ DESCRIPTION ✨

so the manual says: see below tables for the register used in PPL/PPLA clocks ✨ (that's PPL/PPLA, exactly how it's written, don't come for me 🙈)

Regular PLL type — the way this one breaks down:

• Enable → swcr3 → PLLx_SW3_CTRL - BIT[31]
• Config → swcr1 → PLLx_SW1_CTRL - BIT[31:0]
• swcr2 → Not used
• swcr3 → PLLx_SW3_CTRL - BIT[30:0]

Special PLL type A — her whole different era:

• Enable → swcr2 → PLLAx_SW2_CTRL - BIT[16]
• Config → swcr1 → PLLAx_SW1_CTRL - BIT[31:0]
• swcr2 → PLLAx_SW2_CTRL - BIT[15:8]
• swcr3 → PLLAx_SW3_CTRL - BIT[31:0]

and because the original page serves these tables in their raw, unedited, slightly chaotic form (respect honestly 🫡), here they are verbatim so nothing gets lost in translation:

Regular PLL type | Enable | swcr3 | PLLx_SW3_CTRL - BIT[31]    |
----------------------------------------------- | Config | swcr1 |
PLLx_SW1_CTRL - BIT[31:0]  | |        | swcr2 | Not used
| |        | swcr3 | PLLx_SW3_CTRL - BIT[30:0]  |

Special PLL type A | Enable | swcr2 | PLLAx_SW2_CTRL - BIT[16]   |
----------------------------------------------- | Config | swcr1 |
PLLAx_SW1_CTRL - BIT[31:0] | |        | swcr2 | PLLAx_SW2_CTRL -
BIT[15:8] | |        | swcr3 | PLLAx_SW3_CTRL - BIT[31:0] |

ngl the bit fields are giving "read the table twice" energy, so lowkey just match the register and the BIT range and you're slaying 🔥

heads up bestie: the exact bit positions above are the whole spec — don't eyeball them, copy them exactly. no guessing, no improvising, periodt 💀

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✨ SEE ALSO ✨

• Kernel file ./drivers/clk/spacemit/ccu_pll.h — go read the real thing, iykyk 🦋

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and that's the page!! 🎀 source: ./drivers/clk/spacemit, dated October 2026 — mwah, go touch some registers, ily, bye 💜✨