STRUCT AXXIA_PLLCLK(9)

💅 struct axxia_pllclk(9) 💅

okay bestie, we're in the Kernel API Manual, section 9, and today's main character is struct axxia_pllclk — the Axxia PLL generated clock. no cap, this page is short and iconic: it's all about the struct itself and what its members mean. 💖✨

🌸 NAME 🌸

struct axxia_pllclk — the Axxia PLL generated clock. that's the name, that's the vibe, periodt. 🎀

✨ SYNOPSIS ✨

       struct axxia_pllclk {
           struct axxia_clk aclk;
           u32 reg;
        };

🎀 Members 🎀

• aclk — the common struct. the manpage literally calls it Common struct, and that's the whole description, bestie. 🫶
• reg — offset into regmap for the PLL control register. it's giving "here's where the PLL control register sits in regmap" energy. 💅

🌈 SEE ALSO 🌈

if you wanna go down the whole friend-group rabbit hole, the page points you to:

• Kernel file ./drivers/clk/clk-axm5516.c
• struct axxia_clk(9)
• axxia_pllclk_recalc(9)
• struct axxia_divclk(9)
• axxia_divclk_recalc_rate(9)
• struct axxia_clkmux(9)
• axxia_clkmux_get_parent(9)

and that's the whole page, bestie! 🎀 source/version: ./drivers/clk; date: October 2026; footer title: struct axxia_pllclk(9). slay, bye! 💅✨🦋