STRUCT AXIENET_LOCAL(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… struct axienet_local(9) β€” the kernel API manual, but make it make sense

okay bestie, welcome to the lore. this is struct axienet_local β€” the private, per-device data for the axienet driver. yes, ALL of it. grab a snack, we're going member by member ✨


🌸 NAME 🌸

struct axienet_local β€” the axienet private per-device data. it's giving "one struct to hold literally everything" and honestly? iconic.


✨ SYNOPSIS ✨

struct axienet_local {
    struct net_device *ndev;
    struct device *dev;
    struct phylink *phylink;
    struct phylink_config phylink_config;
    struct mdio_device *pcs_phy;
    struct phylink_pcs pcs;
    bool switch_x_sgmii;
    struct clk *axi_clk;
    struct clk_bulk_data misc_clks[XAE_NUM_MISC_CLOCKS];
    struct mii_bus *mii_bus;
    u8 mii_clk_div;
    resource_size_t regs_start;
    void __iomem *regs;
    void __iomem *dma_regs;
    struct napi_struct napi_rx;
    struct dim rx_dim;
    bool rx_dim_enabled;
    u16 rx_irqs;
    spinlock_t rx_cr_lock;
    u32 rx_dma_cr;
    bool rx_dma_started;
    struct axidma_bd *rx_bd_v;
    dma_addr_t rx_bd_p;
    u32 rx_bd_num;
    u32 rx_bd_ci;
    u64_stats_t rx_packets;
    u64_stats_t rx_bytes;
    struct u64_stats_sync rx_stat_sync;
    struct napi_struct napi_tx;
    spinlock_t tx_cr_lock;
    u32 tx_dma_cr;
    bool tx_dma_started;
    struct axidma_bd *tx_bd_v;
    dma_addr_t tx_bd_p;
    u32 tx_bd_num;
    u32 tx_bd_ci;
    u32 tx_bd_tail;
    u64_stats_t tx_packets;
    u64_stats_t tx_bytes;
    struct u64_stats_sync tx_stat_sync;
    u64 hw_stat_base[STAT_COUNT];
    u32 hw_last_counter[STAT_COUNT];
    seqcount_mutex_t hw_stats_seqcount;
    struct mutex stats_lock;
    struct delayed_work stats_work;
    bool reset_in_progress;
    struct work_struct dma_err_task;
    bool stopping;
    int tx_irq;
    int rx_irq;
    int eth_irq;
    phy_interface_t phy_mode;
    u32 options;
    u32 features;
    u32 max_frm_size;
    u32 rxmem;
    u8 use_dmaengine;
    struct dma_chan *tx_chan;
    struct dma_chan *rx_chan;
    struct skbuf_dma_descriptor **tx_skb_ring;
    struct skbuf_dma_descriptor **rx_skb_ring;
    int tx_ring_head;
    int tx_ring_tail;
    int rx_ring_head;
    int rx_ring_tail;
    spinlock_t rx_submit_lock;
 };

πŸŽ€ Members πŸŽ€

bestie. there are a LOT of them. we're doing all of them. no skipping. periodt.

  • ndev β€” pointer for net_device to which it will be attached.
  • dev β€” pointer to the device structure.
  • phylink β€” pointer to the phylink instance.
  • phylink_config β€” the phylink configuration settings.
  • pcs_phy β€” reference to the PCS/PMA PHY, if one is used.
  • pcs β€” the phylink pcs structure for the PCS PHY.
  • switch_x_sgmii β€” whether switchable 1000BaseX/SGMII mode is enabled in the core.
  • axi_clk β€” the AXI4-Lite bus clock.
  • misc_clks β€” misc ethernet clocks (AXI4-Stream, Ref, MGT clocks).
  • mii_bus β€” pointer to the MII bus structure.
  • mii_clk_div β€” the MII bus clock divider value.
  • regs_start β€” resource start for axienet device addresses.
  • regs β€” base address for the axienet_local device address space.
  • dma_regs β€” base address for the axidma device address space.
  • napi_rx β€” NAPI RX control structure.
  • rx_dim β€” DIM state for the receive queue.
  • rx_dim_enabled β€” whether DIM is enabled or not.
  • rx_irqs β€” number of interrupts.
  • rx_cr_lock β€” lock protecting rx_dma_cr, its register, and rx_dma_started.
  • rx_dma_cr β€” nominal content of the RX DMA control register.
  • rx_dma_started β€” set when RX DMA is started.
  • rx_bd_v β€” virtual address of the RX buffer descriptor ring.
  • rx_bd_p β€” physical address (start address) of the RX buffer descr. ring.
  • rx_bd_num β€” size of the RX buffer descriptor ring.
  • rx_bd_ci β€” stores the index of the Rx buffer descriptor in the ring being accessed currently.
  • rx_packets β€” RX packet count for statistics.
  • rx_bytes β€” RX byte count for statistics.
  • rx_stat_sync β€” synchronization object for RX stats.
  • napi_tx β€” NAPI TX control structure.
  • tx_cr_lock β€” lock protecting tx_dma_cr, its register, and tx_dma_started.
  • tx_dma_cr β€” nominal content of the TX DMA control register.
  • tx_dma_started β€” set when TX DMA is started.
  • tx_bd_v β€” virtual address of the TX buffer descriptor ring.
  • tx_bd_p β€” physical address (start address) of the TX buffer descr. ring.
  • tx_bd_num β€” size of the TX buffer descriptor ring.
  • tx_bd_ci β€” stores the next Tx buffer descriptor in the ring that may be complete. only updated at runtime by the TX NAPI poll.
  • tx_bd_tail β€” stores the index of the next Tx buffer descriptor in the ring to be populated.
  • tx_packets β€” TX packet count for statistics.
  • tx_bytes β€” TX byte count for statistics.
  • tx_stat_sync β€” synchronization object for TX stats.
  • hw_stat_base β€” base offset for statistics counters. this may be nonzero if the statistics counters were reset or wrapped around.
  • hw_last_counter β€” last-seen value of each statistic counter.
  • hw_stats_seqcount β€” sequence counter for hw_stat_base, hw_last_counter, and reset_in_progress.
  • stats_lock β€” lock for hw_stats_seqcount.
  • stats_work β€” work for reading the hardware statistics counters often enough to catch overflows.
  • reset_in_progress β€” set while we are performing a reset and statistics counters may be invalid.
  • dma_err_task β€” work structure to process Axi DMA errors.
  • stopping β€” set when we are about to stop the device: makes dma_err_task a no-op (legacy DMA path) and fences RX descriptor resubmission in axienet_dma_rx_cb (dmaengine path).
  • tx_irq β€” Axidma TX IRQ number.
  • rx_irq β€” Axidma RX IRQ number.
  • eth_irq β€” ethernet core IRQ number.
  • phy_mode β€” phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X.
  • options β€” the AxiEthernet option word.
  • features β€” stores the extended features supported by the axienet hw.
  • max_frm_size β€” stores the maximum size of the frame that can be that Txed/Rxed in the existing hardware. if the jumbo option is supported, the maximum frame size would be 9k. else it is 1522 bytes (assuming support for basic VLAN).
  • rxmem β€” stores rx memory size for jumbo frame handling.
  • use_dmaengine β€” flag to check dmaengine framework usage.
  • tx_chan β€” TX DMA channel.
  • rx_chan β€” RX DMA channel.
  • tx_skb_ring β€” pointer to the TX skb ring buffer array.
  • rx_skb_ring β€” pointer to the RX skb ring buffer array.
  • tx_ring_head β€” TX skb ring buffer head index.
  • tx_ring_tail β€” TX skb ring buffer tail index.
  • rx_ring_head β€” RX skb ring buffer head index.
  • rx_ring_tail β€” RX skb ring buffer tail index.
  • rx_submit_lock β€” protects RX ring resubmission vs teardown in the dmaengine path.
lowkey the stopping, reset_in_progress, and hw_stats_seqcount trio is the whole "don't read stats mid-reset" safety net, bestie. respect the locks. πŸ’…

πŸ‘‘ SEE ALSO πŸ‘‘

go read the kernel file ./drivers/net/ethernet/xilinx/xilinx_axienet.h, plus these little icons: struct axidma_bd(9), struct skbuf_dma_descriptor(9), struct axienet_option(9), axienet_ior(9), axienet_iow(9), axienet_dma_out32(9), axienet_dma_out64(9) β€” iykyk 🌈


🫢 and that's the page, bestie β€” brought to you by the source at ./drivers/net/ethernet/xilinx and dated October 2026. no cap, go read the other pages too. πŸ’–πŸŽ€πŸ¦‹

πŸ“¦ where this page comes from