STRUCT ATMEL_PIOCTRL(9)
β¨ struct atmel_pioctrl(9) β¨
okay bestie, so this is from the Kernel API Manual β a whole struct atmel_pioctrl, which is literally the Atmel PIO controller (pinmux + gpio). it's giving "one struct to rule them all" and honestly? iconic. π
π NAME π
struct atmel_pioctrl β the Atmel PIO controller, doing double duty as pinmux + gpio. yes ma'am, both. π
πΈ SYNOPSIS πΈ
struct atmel_pioctrl {
void __iomem *reg_base;
struct clk *clk;
unsigned int nbanks;
struct pinctrl_dev *pinctrl_dev;
struct atmel_group *groups;
const char * const *group_names;
struct atmel_pin **pins;
unsigned int npins;
struct gpio_chip *gpio_chip;
struct irq_domain *irq_domain;
int *irqs;
unsigned int *pm_wakeup_sources;
struct {
u32 imr;
u32 odsr;
u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];
} *pm_suspend_backup;
struct device *dev;
struct device_node *node;
unsigned int slew_rate_support;
};
no cap, that's the whole shape of it. let's go member by member π«Ά
π¦ Members π¦
reg_baseβ base address of the controller. the home address, if you will πclkβ clock of the controller. it's the heartbeat, fr fr β°nbanksβ number of PIO groups. heads up: it can vary depending on the SoC, so don't come for me if your board's count is different πpinctrl_devβ the pinctrl device that got registered.groupsβ the groups table, there to provide group name and pin in the group to pinctrl. very "here's your label, here's your pin" energy π·οΈgroup_namesβ group names table, providing all the group/pin names to pinctrl or gpio. sharing is caring.pinsβ pins table, used for both pinctrl and gpio. thepin_id,bankandlinefields are set at probe time; the other ones are set when parsing dt pinctrl. so it's a two-phase glow-up β¨npinsβ number of pins, periodt.gpio_chipβ the gpio chip that got registered.irq_domainβ irq domain for the gpio controller. interrupt royalty πirqsβ table containing the hw irq number of the bank. and the index of the table is the bank id β iykyk π₯pm_wakeup_sourcesβ bitmap of wakeup sources (lines).pm_suspend_backupβ backup/restore register values on suspend/resume. it remembers so you don't have to π inside it livesu32 imr,u32 odsr, andu32 cfgr[ATMEL_PIO_NPINS_PER_BANK].devβ device entry for the Atmel PIO controller.nodeβ node of the Atmel PIO controller.slew_rate_supportβ slew rate support. yes that's the whole description and yes we're keeping it π
π SEE ALSO π
- Kernel file
./drivers/pinctrl/pinctrl-at91-pio4.c struct atmel_pioctrl_data(9)
and that's the vibe check, bestie π§ source lives under ./drivers/pinctrl, dated October 2026 β struct atmel_pioctrl(9), signed, sealed, slayed. π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms