STRUCT ASPEED_CLK_GATE(9)

💖 struct aspeed_clk_gate(9) 💖

okay so bestie, welcome to the struct aspeed_clk_gate(9) page in the Kernel API Manual — this is the little glow-up version of clk_gate that Aspeed SoCs needed, and honestly? iconic. 🎀

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✨ NAME ✨

struct aspeed_clk_gate — the Aspeed-specific clk_gate structure. that's it, that's the vibe. 💅

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🌸 SYNOPSIS 🌸

struct aspeed_clk_gate {
    struct clk_hw   hw;
    struct regmap   *map;
    u8 clock_idx;
    s8 reset_idx;
    u8 flags;
    spinlock_t *lock;
 };

look at her. six fields. no notes. 😌

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🦋 Members 🦋

• hw — the handle that sits between the common clk interfaces and the hardware-specific ones. lowkey the social liaison of the struct. 🫶
• clock_idx — the bit used to gate this clock in the clock register. that's the on/off switch, bestie. 🔥
• reset_idx — the bit used to reset this IP in the reset register. and listen: it's -1 if no reset is required when enabling the clock. don't forget the -1, she matters. 💀
• flags — hardware-specific flags. mystery lil flags. 🎀
• lock — the register lock. keeps everything from getting messy. 🔒✨

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🌈 Description 🌈

so here's the tea ☕ — some of the clocks in the Aspeed SoC literally have to be put in reset before enabling. like, that's the requirement, no cap.

this modified version of clk_gate is the one that lets you specify an optional reset bit, so the hardware gets what the hardware needs. slay. 👑

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⭐ SEE ALSO ⭐

• Kernel file ./drivers/clk/aspeed/clk-aspeed.h struct aspeed_gate_data(9), struct aspeed_reset(9), struct aspeed_clk_soc_data(9)

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fr fr, go read those other structs too, they're all in the same friend group. 🧚💜

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mwah 💋 this page lives at ./drivers/clk/aspeed, dated October 2026, and it's brought to you by struct aspeed_clk_gate(9) — the manual page that ate and left no crumbs. 🌸🦋💖