STRUCT ASIC_FIXED_PROPERTIES(9)

🎀 struct asic_fixed_properties(9) 🎀

okay bestie, welcome to the Kernel API Manual entry for struct asic_fixed_properties(9) — it's the ASIC-specific immutable-properties struct, and it's giving “the hardware sat me down and told me its whole life story” energy. 💅 no cap, every field matters here.

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🌸 NAME 🌸

struct asic_fixed_properties — ASIC specific immutable properties.

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✨ SYNOPSIS ✨

here's the exact struct, copied with love and zero edits:

struct asic_fixed_properties {
    struct hw_queue_properties      *hw_queues_props;
    struct hl_special_block_info    *special_blocks;
    struct hl_skip_blocks_cfg       skip_special_blocks_cfg;
    struct cpucp_info               cpucp_info;
    char uboot_ver[VERSION_MAX_LEN];
    char preboot_ver[VERSION_MAX_LEN];
    struct hl_mmu_properties        dmmu;
    struct hl_mmu_properties        pmmu;
    struct hl_mmu_properties        pmmu_huge;
    struct hl_hints_range           hints_dram_reserved_va_range;
    struct hl_hints_range           hints_host_reserved_va_range;
    struct hl_hints_range           hints_host_hpage_reserved_va_range;
    u64 sram_base_address;
    u64 sram_end_address;
    u64 sram_user_base_address;
    u64 dram_base_address;
    u64 dram_end_address;
    u64 dram_user_base_address;
    u64 dram_size;
    u64 dram_pci_bar_size;
    u64 max_power_default;
    u64 dc_power_default;
    u64 dram_size_for_default_page_mapping;
    u64 pcie_dbi_base_address;
    u64 pcie_aux_dbi_reg_addr;
    u64 mmu_pgt_addr;
    u64 mmu_dram_default_page_addr;
    u64 tpc_enabled_mask;
    u64 tpc_binning_mask;
    u64 dram_enabled_mask;
    u64 dram_binning_mask;
    u64 dram_hints_align_mask;
    u64 cfg_base_address;
    u64 mmu_cache_mng_addr;
    u64 mmu_cache_mng_size;
    u64 device_dma_offset_for_host_access;
    u64 host_base_address;
    u64 host_end_address;
    u64 max_freq_value;
    u64 engine_core_interrupt_reg_addr;
    u32 clk_pll_index;
    u32 mmu_pgt_size;
    u32 mmu_pte_size;
    u32 dram_page_size;
    u32 cfg_size;
    u32 sram_size;
    u32 max_asid;
    u32 num_of_events;
    u32 psoc_pci_pll_nr;
    u32 psoc_pci_pll_nf;
    u32 psoc_pci_pll_od;
    u32 psoc_pci_pll_div_factor;
    u32 psoc_timestamp_frequency;
    u32 high_pll;
    u32 cb_pool_cb_cnt;
    u32 cb_pool_cb_size;
    u32 decoder_enabled_mask;
    u32 decoder_binning_mask;
    u32 rotator_enabled_mask;
    u32 edma_enabled_mask;
    u32 edma_binning_mask;
    u32 max_pending_cs;
    u32 max_queues;
    u32 fw_preboot_cpu_boot_dev_sts0;
    u32 fw_preboot_cpu_boot_dev_sts1;
    u32 fw_bootfit_cpu_boot_dev_sts0;
    u32 fw_bootfit_cpu_boot_dev_sts1;
    u32 fw_app_cpu_boot_dev_sts0;
    u32 fw_app_cpu_boot_dev_sts1;
    u32 max_dec;
    u32 hmmu_hif_enabled_mask;
    u32 faulty_dram_cluster_map;
    u32 xbar_edge_enabled_mask;
    u32 device_mem_alloc_default_page_size;
    u32 num_engine_cores;
    u32 max_num_of_engines;
    u32 num_of_special_blocks;
    u32 glbl_err_max_cause_num;
    u32 hbw_flush_reg;
    u32 reserved_fw_mem_size;
    u32 fw_event_queue_size;
    u16 collective_first_sob;
    u16 collective_first_mon;
    u16 sync_stream_first_sob;
    u16 sync_stream_first_mon;
    u16 first_available_user_sob[HL_MAX_DCORES];
    u16 first_available_user_mon[HL_MAX_DCORES];
    u16 first_available_user_interrupt;
    u16 first_available_cq[HL_MAX_DCORES];
    u16 user_interrupt_count;
    u16 user_dec_intr_count;
    u16 tpc_interrupt_id;
    u16 eq_interrupt_id;
    u16 cache_line_size;
    u16 server_type;
    u8 completion_queues_count;
    u8 completion_mode;
    u8 mme_master_slave_mode;
    u8 fw_security_enabled;
    u8 fw_cpu_boot_dev_sts0_valid;
    u8 fw_cpu_boot_dev_sts1_valid;
    u8 dram_supports_virtual_memory;
    u8 hard_reset_done_by_fw;
    u8 num_functional_hbms;
    u8 hints_range_reservation;
    u8 iatu_done_by_fw;
    u8 dynamic_fw_load;
    u8 gic_interrupts_enable;
    u8 use_get_power_for_reset_history;
    u8 supports_compute_reset;
    u8 allow_inference_soft_reset;
    u8 configurable_stop_on_err;
    u8 set_max_power_on_device_init;
    u8 supports_user_set_page_size;
    u8 dma_mask;
    u8 supports_advanced_cpucp_rc;
    u8 supports_engine_modes;
    u8 support_dynamic_resereved_fw_size;
    u8 supports_nvme;
};

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💅 Members 💅

okay so this is the member-by-member tea, and we are not skipping a single one. 🫶

• hw_queues_props — the H/W queues properties.
• special_blocks — points to an array containing special blocks info. yes, an array, and yes, they're special.
• skip_special_blocks_cfg — special blocks skip configs.
• cpucp_info — all the various information received from CPU-CP regarding the H/W, e.g. available sensors.
• uboot_ver — the F/W U-boot version.
• preboot_ver — the F/W Preboot version.
• dmmu — DRAM MMU address translation properties.
• pmmu — PCI (host) MMU address translation properties.
• pmmu_huge — PCI (host) MMU address translation properties for memory allocated with huge pages.
• hints_dram_reserved_va_range — the dram hint addresses reserved range.
• hints_host_reserved_va_range — the host hint addresses reserved range.
• hints_host_hpage_reserved_va_range — the host huge page hint addresses reserved range.
• sram_base_address — SRAM physical start address.
• sram_end_address — SRAM physical end address.
• sram_user_base_address — SRAM physical start address for user access.
• dram_base_address — DRAM physical start address.
• dram_end_address — DRAM physical end address.
• dram_user_base_address — DRAM physical start address for user access.
• dram_size — DRAM total size.
• dram_pci_bar_size — size of PCI bar towards DRAM.
• max_power_default — max power of the device after reset.
• dc_power_default — power consumed by the device in mode idle.
• dram_size_for_default_page_mapping — DRAM size needed to map to avoid page fault.
• pcie_dbi_base_address — Base address of the PCIE_DBI block.
• pcie_aux_dbi_reg_addr — Address of the PCIE_AUX DBI register.
• mmu_pgt_addr — base physical address in DRAM of MMU page tables.
• mmu_dram_default_page_addr — DRAM default page physical address.
• tpc_enabled_mask — which TPCs are enabled.
• tpc_binning_mask — which TPCs are binned. 0 means usable and 1 means binned.
• dram_enabled_mask — which DRAMs are enabled.
• dram_binning_mask — which DRAMs are binned. 0 means usable, 1 means binned.
• dram_hints_align_mask — dram va hint addresses alignment mask which is used for hints validity check.
• cfg_base_address — config space base address.
• mmu_cache_mng_addr — address of the MMU cache.
• mmu_cache_mng_size — size of the MMU cache.
• device_dma_offset_for_host_access — the offset to add to host DMA addresses to enable the device to access them.
• host_base_address — host physical start address for host DMA from device.
• host_end_address — host physical end address for host DMA from device.
• max_freq_value — current max clk frequency.
• engine_core_interrupt_reg_addr — interrupt register address for engine core to use in order to raise events toward FW.
• clk_pll_index — clock PLL index that says which PLL determines the clock we display to the user.
• mmu_pgt_size — MMU page tables total size.
• mmu_pte_size — PTE size in MMU page tables.
• dram_page_size — The DRAM physical page size.
• cfg_size — configuration space size on SRAM.
• sram_size — total size of SRAM.
• max_asid — maximum number of open contexts (ASIDs).
• num_of_events — number of possible internal H/W IRQs.
• psoc_pci_pll_nr — PCI PLL NR value.
• psoc_pci_pll_nf — PCI PLL NF value.
• psoc_pci_pll_od — PCI PLL OD value.
• psoc_pci_pll_div_factor — PCI PLL DIV FACTOR 1 value.
• psoc_timestamp_frequency — frequency of the psoc timestamp clock.
• high_pll — high PLL frequency used by the device.
• cb_pool_cb_cnt — number of CBs in the CB pool.
• cb_pool_cb_size — size of each CB in the CB pool.
• decoder_enabled_mask — which decoders are enabled.
• decoder_binning_mask — which decoders are binned, 0 means usable and 1 means binned.
• rotator_enabled_mask — which rotators are enabled.
• edma_enabled_mask — which EDMAs are enabled.
• edma_binning_mask — which EDMAs are binned, 0 means usable and 1 means binned (at most one binned DMA).
• max_pending_cs — maximum of concurrent pending command submissions.
• max_queues — maximum amount of queues in the system.
• fw_preboot_cpu_boot_dev_sts0 — bitmap representation of preboot cpu capabilities reported by FW, bit description can be found in CPU_BOOT_DEV_STS0.
• fw_preboot_cpu_boot_dev_sts1 — bitmap representation of preboot cpu capabilities reported by FW, bit description can be found in CPU_BOOT_DEV_STS1.
• fw_bootfit_cpu_boot_dev_sts0 — bitmap representation of boot cpu security status reported by FW, bit description can be found in CPU_BOOT_DEV_STS0.
• fw_bootfit_cpu_boot_dev_sts1 — bitmap representation of boot cpu security status reported by FW, bit description can be found in CPU_BOOT_DEV_STS1.
• fw_app_cpu_boot_dev_sts0 — bitmap representation of application security status reported by FW, bit description can be found in CPU_BOOT_DEV_STS0.
• fw_app_cpu_boot_dev_sts1 — bitmap representation of application security status reported by FW, bit description can be found in CPU_BOOT_DEV_STS1.
• max_dec — maximum number of decoders.
• hmmu_hif_enabled_mask — mask of HMMUs/HIFs that are not isolated (enabled) 1-enabled, 0- isolated.
• faulty_dram_cluster_map — mask of faulty DRAM cluster. 1- faulty cluster, 0- good cluster.
• xbar_edge_enabled_mask — mask of XBAR_EDGEs that are not isolated (enabled) 1-enabled, 0- isolated.
• device_mem_alloc_default_page_size — the default page size for device memory allocation ✨ and heads up: this can be different from dram_page_size only for ASICs where supports_user_set_page_size is true (like, only when the DRAM actually supports multiple page sizes, iykyk). Otherwise it shall be equal to dram_page_size — no wiggle room bestie 💅
• num_engine_cores — how many engine CPU cores there are 🔥
• max_num_of_engines — the absolute max number of all engines in the ASIC 👑
• num_of_special_blocks — the size of the special_blocks array 🎀
• glbl_err_max_cause_num — the max cause number for global errors 💀
• hbw_flush_reg — the register you read to generate an HBW flush. A value of 0 means HBW flush just… isn't supported 🙈
• reserved_fw_mem_size — how much DRAM memory is reserved for FW 🧚
• fw_event_queue_size — queue size for events coming from CPU-CP. A value of 0 means "just use the default HL_EQ_SIZE_IN_BYTES value" 🌸
• collective_first_sob — the first sync object available for collective use
• collective_first_mon — the first monitor available for collective use
• sync_stream_first_sob — the first sync object available for sync stream use
• sync_stream_first_mon — the first monitor available for sync stream use
• first_available_user_sob — the first sob that's available for the user 🫶
• first_available_user_mon — the first monitor that's available for the user
• first_available_user_interrupt — the first available interrupt reserved for the user ⭐
• first_available_cq — the first available CQ for the user 💜
• user_interrupt_count — the number of user interrupts
• user_dec_intr_count — how many decoder interrupts are exposed to the user
• tpc_interrupt_id — the interrupt id TPC uses to raise events towards the host 📣
• eq_interrupt_id — the interrupt id for EQ, used to synchronize EQ interrupts during hard-reset
• cache_line_size — the device cache line size 🦋
• server_type — the server type this ASIC is currently installed in. The value follows enum hl_server_type in the uapi file
• completion_queues_count — the number of completion queues
• completion_mode — 0 = job based completion, 1 = cs based completion ✨
• mme_master_slave_mode — 0 = each MME works independently, 1 = MME works in Master/Slave mode 👯
• fw_security_enabled — true if security measures are enabled in firmware, false otherwise 🔒
• fw_cpu_boot_dev_sts0_valid — the status bits are valid and can be fetched from BOOT_DEV_STS0
• fw_cpu_boot_dev_sts1_valid — the status bits are valid and can be fetched from BOOT_DEV_STS1
• dram_supports_virtual_memory — is there actually an MMU towards the DRAM 👀
• hard_reset_done_by_fw — true if firmware is the one handling the hard reset flow 💀
• num_functional_hbms — the number of functional HBMs in each DCORE
• hints_range_reservation — does the device support hint addresses range reservation 🎀
• iatu_done_by_fw — true if iATU configuration is being done by FW
• dynamic_fw_load — is dynamic FW load supported 🌈
• gic_interrupts_enable — true if FW is not blocking the GIC controller, false otherwise
• use_get_power_for_reset_history — for backward compatibility with Goya and Gaudi 🫶
• supports_compute_reset — is a reset that is not a hard-reset supported by this asic
• allow_inference_soft_reset — true if the ASIC supports a soft reset initiated by the user or by TDR. This is only true in inference ASICs, because there's literally no real-world use-case for doing a soft-reset in training (training runs on multiple devices, so yeah 😭) 💅
• configurable_stop_on_err — is the stop-on-error option configurable via debugfs
• set_max_power_on_device_init — true if max power needs to be set in F/W on device init ⚡
• supports_user_set_page_size — true if the user can set the allocation page size
• dma_mask — the dma mask to set for this device 🦋
• supports_advanced_cpucp_rc — true if the new cpucp opcodes are supported
• supports_engine_modes — true if changing engines/engine_cores modes is supported 👑
• support_dynamic_resereved_fw_size — true if we support dynamic reserved size for fw (yes, that spelling is exactly what the struct says, no cap 🫶)
• supports_nvme — tells you whether the asic supports NVMe P2P DMA 🔥

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💖 SEE ALSO 💖

Kernel file ./drivers/accel/habanalabs/common/habanalabs.h 🗂️ and literally the entire extended fam:

• enum hl_mmu_page_table_location(9)
• struct iterate_module_ctx(9)
• struct hl_gen_wait_properties(9)
• struct pgt_info(9)
• enum hl_pci_match_mode(9)
• enum hl_fw_component(9)
• enum hl_fw_types(9)
• enum hl_queue_type(9)
• struct hw_queue_properties(9)
• enum vm_type(9)
• enum mmu_op_flags(9)
• enum hl_device_hw_state(9)
• struct hl_mmu_properties(9)
• struct hl_hints_range(9)
• struct hl_fence(9)
• struct hl_cs_compl(9)
• struct hl_ts_buff(9)
• struct hl_mem_mgr(9)
• struct hl_mem_mgr_fini_stats(9)
• struct hl_mmap_mem_buf_behavior(9)
• struct hl_mmap_mem_buf(9)
• struct hl_cb(9)
• struct hl_sync_stream_properties(9)
• struct hl_encaps_signals_mgr(9)
• struct hl_hw_queue(9)
• struct hl_cq(9)
• struct hl_ts_free_jobs(9)
• struct hl_user_interrupt(9)
• struct timestamp_reg_free_node(9)
• struct hl_user_pending_interrupt(9)
• struct hl_eq(9)
• struct hl_dec(9)
• enum hl_asic_type(9)
• enum hl_pm_mng_profile(9)
• enum hl_pll_frequency(9)
• struct pci_mem_region(9)
• struct static_fw_load_mgr(9)
• struct fw_response(9)
• struct dynamic_fw_load_mgr(9)
• struct pre_fw_load_props(9)
• struct fw_image_props(9)
• struct fw_load_mgr(9)
• struct engines_data(9)
• struct hl_asic_funcs(9)
• enum hl_va_range_type(9)
• struct hl_va_range(9)
• struct hl_cs_counters_atomic(9)
• struct hl_dmabuf_priv(9)
• struct hl_cs_outcome(9)
• struct hl_cs_outcome_store(9)
• struct hl_ctx(9)
• struct hl_ctx_mgr(9)
• struct hl_userptr(9)
• struct hl_cs(9)
• struct hl_cs_job(9)
• struct hl_cs_parser(9)
• struct hl_vm_hash_node(9)
• struct hl_vm_hw_block_list_node(9)
• struct hl_vm_phys_pg_pack(9)
• struct hl_vm_va_block(9)
• struct hl_vm(9)
• struct hl_debug_params(9)
• struct hl_notifier_event(9)
• struct hl_fpriv(9)
• struct hl_info_list(9)
• struct hl_debugfs_entry(9)
• struct hl_dbg_device_entry(9)
• struct hl_debugfs_cfg_access_entry(9)
• struct hl_debugfs_cfg_access(9)
• struct hl_hw_obj_name_entry(9)
• struct hl_mon_state_dump(9)
• struct hl_sync_to_engine_map_entry(9)
• struct hl_sync_to_engine_map(9)
• struct hl_state_dump_specs_funcs(9)
• struct hl_state_dump_specs(9)
• struct hl_device_reset_work(9)
• struct hl_mmu_priv(9)
• struct hl_mmu_per_hop_info(9)
• struct hl_mmu_hop_info(9)
• struct hl_hr_mmu_funcs(9)
• struct hl_mmu_funcs(9)
• struct hl_prefetch_work(9)
• struct multi_cs_completion(9)
• struct multi_cs_data(9)
• struct hl_clk_throttle_timestamp(9)
• struct hl_clk_throttle(9)
• struct user_mapped_block(9)
• struct cs_timeout_info(9)
• struct undefined_opcode_info(9)
• struct page_fault_info(9)
• struct razwi_info(9)
• struct hw_err_info(9)
• struct fw_err_info(9)
• struct engine_err_info(9)
• struct hl_error_info(9)
• struct hl_reset_info(9)
• struct eq_heartbeat_debug_info(9)
• struct hl_device(9)
• struct hl_cs_encaps_sig_handle(9)
• struct hl_info_fw_err_info(9)
• hl_ioctl_t(9)
• struct hl_ioctl_desc(9)
• hl_get_sg_info(9)
• hl_mem_area_inside_range(9)
• hl_mem_area_crosses_range(9)

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That's a wrap on the struct, bestie — go forth and slay 💅✨ This one lives in ./drivers/accel/habanalabs/common, dated October 2026, and it's page struct asic_...d_properties(9) in the Kernel API Manual. mwah 🫶🎀💖