STRUCT ANAND(9)

๐Ÿ“ฆ version 7.3.1, in nixpkgs unstable

๐Ÿ’– struct anand(9) ๐Ÿ’–

okay so welcome to the Kernel API Manual, bestie โ€” today's main character is struct anand, and its whole personality is "I define the NAND chip related information." that's it, that's the vibe. it's giving โœจ documentation โœจ and honestly? we're obsessed. ๐ŸŽ€


โœจ NAME โœจ

struct anand โ€” literally defines the NAND chip related information. no cap, that's the whole job. ๐Ÿ‘‘


๐Ÿฆ‹ SYNOPSIS ๐Ÿฆ‹

here's the glow-up in code form, copied exactly, don't touch a single character or i will cry:

struct anand {
    struct list_head node;
    struct nand_chip chip;
    unsigned int rb;
    unsigned int page_sz;
    unsigned long clk;
    u32 data_iface;
    u32 timings;
    u32 ecc_conf;
    u32 strength;
    u16 raddr_cycles;
    u16 caddr_cycles;
    unsigned int ecc_bits;
    unsigned int ecc_total;
    unsigned int *errloc;
    u8 *hw_ecc;
    struct bch_control *bch;
    int *cs_idx;
    int ncs_idx;
 };

likeโ€ฆ she's structured. she's organized. she has range. ๐Ÿ’…


๐ŸŒธ Members ๐ŸŒธ

okay now the meet-the-cast section, gather round besties ๐Ÿซถ

  • node โ€” used to store NAND chips into a list. she's a social queen, she links the whole friend group together. ๐Ÿ”—
  • chip โ€” the NAND chip information structure. the whole info dump, iconically. ๐Ÿ“‹
  • rb โ€” ready-busy line. the "are you done yet??" wire. โณ
  • page_sz โ€” register value of the page_sz field to use. the exact value you're plugging in. ๐Ÿ“
  • clk โ€” expected clock frequency to use. the tempo, the BPM, the heartbeat of the whole operation. ๐Ÿ’“
  • data_iface โ€” data interface timing mode to use. pick your mode, bestie. ๐ŸŽ›๏ธ
  • timings โ€” NV-DDR specific timings to use. very specific, very fancy. โšก
  • ecc_conf โ€” hardware ECC configuration value. the error-correcting config, slay. ๐Ÿ› ๏ธ
  • strength โ€” register value of the ECC strength. how hard the ECC goes. ๐Ÿ’ช
  • raddr_cycles โ€” row address cycle information. ๐Ÿงญ
  • caddr_cycles โ€” column address cycle information. ๐Ÿ“
  • ecc_bits โ€” exact number of ECC bits per syndrome. exact, no guesses, periodt. ๐Ÿ”ข
  • ecc_total โ€” total number of ECC bytes. the whole bag. ๐ŸŽ’
  • errloc โ€” array of errors located with soft BCH. the naughty list, basically ๐Ÿ˜ญ
  • hw_ecc โ€” buffer to store syndromes computed by hardware. hardware did the math, this holds the receipts. ๐Ÿงพ
  • bch โ€” BCH structure. justโ€ฆ the BCH structure. iconic in its brevity. ๐ŸŒˆ
  • cs_idx โ€” array of chip-select for this device, values are indexes of the controller structure gpio_cs array. yes, indexes of the gpio_cs array, we said what we said. ๐Ÿ”Ž
  • ncs_idx โ€” size of the cs_idx array. someone has to keep count. ๐Ÿงฎ
fr fr every member above is exactly as documented โ€” nothing added, nothing skipped, no invented lore. i would never. ๐Ÿ™ˆ

๐Ÿ‘‘ SEE ALSO ๐Ÿ‘‘

go touch some other kernel files, bestie:

  • Kernel file ./drivers/mtd/nand/raw/arasan-nand-controller.c
  • struct anfc_op(9)
  • struct arasan_nfc(9)

and that's the whole page, mwah ๐Ÿ’‹ this lil love letter lives in ./drivers/mtd/nand/raw and it's dated October 2026 โ€” so mark your calendar, screenshot it, put it on your story, whatever. bye bestie, go read a struct! ๐ŸŒŸ

๐Ÿ“ฆ where this page comes from