STRUCT AMDGPU_DISPLAY_MANAGER(9)

💖 NAME 💖

Okay bestie, this is the struct amdgpu_display_manager page from the Kernel API Manual — manual name struct amdgpu_display_manager(9) — and it’s literally the central amdgpu display manager device. One big struct, whole lotta display-manager glue, main character energy. 🫶

✨ SYNOPSIS ✨

Here’s the struct in all its glory — exact fields, exact names, no “I fixed the spacing” nonsense, bestie 💅

struct amdgpu_display_manager {
    struct dc *dc;
    struct dmub_srv *dmub_srv;
    struct dmub_notification *dmub_notify;
    dmub_notify_interrupt_callback_t
dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX];
    bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX];
    struct dmub_srv_fb_info *dmub_fb_info;
    const struct firmware *dmub_fw;
    struct amdgpu_bo *dmub_bo;
    u64 dmub_bo_gpu_addr;
    void *dmub_bo_cpu_addr;
    uint32_t dmcub_fw_version;
    uint32_t fw_inst_size;
    struct cgs_device *cgs_device;
    struct amdgpu_device *adev;
    struct drm_device *ddev;
    u16 display_indexes_num;
    struct drm_private_obj atomic_obj;
    struct mutex dc_lock;
    spinlock_t dmub_lock;
    struct mutex audio_lock;
    struct drm_audio_component *audio_component;
    bool audio_registered;
    struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
    struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
    struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST -
DC_IRQ_SOURCE_PFLIP_FIRST + 1];
    struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 -
DC_IRQ_SOURCE_VBLANK1 + 1];
    struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 -
DC_IRQ_SOURCE_DC1_VLINE0 + 1];
    struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 -
DC_IRQ_SOURCE_VUPDATE1 + 1];
    spinlock_t irq_reg_lock;
    struct common_irq_params dmub_trace_params[1];
    struct common_irq_params dmub_outbox_params[1];
    spinlock_t irq_handler_list_table_lock;
    struct workqueue_struct *irq_wq;
    struct workqueue_struct *vmin_vmax_wq;
    struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP];
    const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];
    uint8_t num_of_edps;
    struct amdgpu_dm_backlight_caps
backlight_caps[AMDGPU_DM_MAX_NUM_EDP];
    struct mod_freesync *freesync_module;
    struct mod_power *power_module;
    struct hdcp_workqueue *hdcp_workqueue;
    struct workqueue_struct *vblank_control_workqueue;
    struct idle_workqueue *idle_workqueue;
    struct drm_atomic_commit *cached_state;
    struct dc_state *cached_dc_state;
    struct dm_compressor_info compressor;
    const struct firmware *fw_dmcu;
    uint32_t dmcu_fw_version;
    const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
    uint32_t active_vblank_irq_count;
  #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY);
    struct secure_display_context secure_display_ctx;
  #endif;
    struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq;
    struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
    bool force_timing_sync;
    bool disable_hpd_irq;
    bool dmcub_trace_event_en;
    struct list_head da_list;
    struct completion dmub_aux_transfer_done;
    struct workqueue_struct *delayed_hpd_wq;
    u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
    u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];
    bool aux_hpd_discon_quirk;
    bool edp0_on_dp1_quirk;
    struct mutex dpia_aux_lock;
    void *bb_from_dmub;
    void *i2c_devres_group;
    struct amdgpu_i2c_adapter *oem_i2c;
    struct fused_io_sync {
      struct completion replied;
      char reply_data[0x40];
    } fused_io[8];
    struct workqueue_struct *hdmi_frl_status_polling_wq;
    struct delayed_work hdmi_frl_status_polling_work;
    unsigned int hdmi_frl_status_polling_delay_ms;
    struct dm_boot_time_crc_info boot_time_crc_info;
};

Quick heads-up, bestie: power_module, hdmi_frl_status_polling_wq, hdmi_frl_status_polling_delay_ms, and boot_time_crc_info are all in the struct above, but the original Members list doesn’t describe those — so I’m not inventing lore, they’re just chilling in the code block 🫶

🫶 Members 🫶

Members time — this is the cast of characters. Every technical detail stays exactly where it belongs; I’m just giving it group-chat energy. 💖

• dc — Display Core control structure. Main character of the display-core situation ✨
• dmub_srv — DMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it. 💅
• dmub_notify — notification from DMUB. 📬
• dmub_callback — callback functions to handle notification from DMUB. 🎀
• dmub_thread_offload — flag to indicate if callback is offload. ✅
• dmub_fb_info — framebuffer regions for the DMUB. 🖼️
• dmub_fw — DMUB firmware, required on hardware that has DMUB support. 🔥
• dmub_bo — buffer object for the DMUB. 🧸
• dmub_bo_gpu_addr — GPU virtual address for the DMUB buffer object. 🛰️
• dmub_bo_cpu_addr — CPU address for the DMUB buffer object. 🧠
• dmcub_fw_version — DMCUB firmware version. 🏷️
• fw_inst_size — size of the firmware instruction buffer. 📏
• cgs_device — the Common Graphics Services device. It provides an interface for accessing registers. 🎛️
• adev — AMDGPU base driver structure. 🧱
• ddev — DRM base driver structure. 🎬
• display_indexes_num — max number of display streams supported. 🔢
• atomic_obj — in combination with dm_atomic_state it helps manage global atomic state that doesn’t map cleanly into existing drm resources, like dc_context. 🌀
• dc_lock — guards access to DC functions that can issue register write sequences. 🔒
• dmub_lock — guards access to DMUB command submission. 🛡️
• audio_lock — guards access to audio instance changes. 🔊
• audio_component — used to notify ELD changes to sound driver. 🎧
• audio_registered — true if the audio component has been registered successfully, false otherwise. ✅
• irq_handler_list_low_tab — low priority IRQ handler table. It is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep. Note that handlers are called in the same order as they were registered (FIFO). 😴
• irq_handler_list_high_tab — high priority IRQ handler table. It is a n*m table, same as irq_handler_list_low_tab. However, handlers in this table are not deferred and are called immediately. ⚡
• pflip_params — page flip IRQ parameters, passed to registered handlers when triggered. 🔄
• vblank_params — vertical blanking IRQ parameters, passed to registered handlers when triggered. 🌙
• vline0_params — OTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered. 📍
• vupdate_params — vertical update IRQ parameters, passed to registered handlers when triggered. 🔁
• irq_reg_lock — serializes the read-modify-writes of the HW interrupt control registers. Several interrupt sources share one register — e.g. the enable and clear bits of both VSTARTUP (vblank) and VUPDATE_NO_LOCK live in OTG_GLOBAL_SYNC_STATUS. Therefore, enabling one source must not race with acking another. Held only across amdgpu_dm_irq_set and amdgpu_dm_irq_ack. 🧨
• dmub_trace_params — DMUB trace event IRQ parameters, passed to registered handlers when triggered. 🧵
• dmub_outbox_params — DMUB Outbox parameters. 📤
• irq_handler_list_table_lock — synchronizes access to IRQ tables. 🔐
• irq_wq — dedicated high-priority unbound workqueue for deferred IRQ work. ⚙️
• vmin_vmax_wq — dedicated unbound workqueue for deferred vmin/vmax updates. 📈
• backlight_dev — backlight control device. 💡
• backlight_link — link on which to control backlight. 🔗
• num_of_edps — number of backlight eDPs. 🖥️
• backlight_caps — capabilities of the backlight device. 🎚️
• freesync_module — module handling freesync calculations. 🌀
• hdcp_workqueue — AMDGPU content protection queue. 🛡️
• vblank_control_workqueue — deferred work for vblank control events. 🌙
• idle_workqueue — periodic work for idle events. 💤
• cached_state — caches device atomic state for suspend/resume. 💾
• cached_dc_state — cached state of content streams. 🎞️
• compressor — frame buffer compression buffer. See struct dm_compressor_info. 🗜️
• fw_dmcu — reference to DMCU firmware. 📦
• dmcu_fw_version — version of the DMCU firmware. 🏷️
• soc_bounding_box — gpu_info FW provided soc bounding box struct or 0 if not available in FW. 📦
• active_vblank_irq_count — number of currently active vblank irqs. 🔢
• secure_display_ctx — store secure display relevant info. e.g. the ROI information, the work_struct to command dmub, etc. 🔐
• hpd_rx_offload_wq — work queue to offload works of hpd_rx_irq. 📥
• mst_encoders — fake encoders used for DP MST. 🎭
• force_timing_sync — set via debugfs. When set, indicates that all connected displays will be forced to synchronize. 🔄
• disable_hpd_irq — disables all HPD and HPD RX interrupt handling in the driver when true. 🚫
• dmcub_trace_event_en — enable dmcub trace events. 🧵
• da_list — DAL fb memory allocation list, for communication with SMU. 📋
• dmub_aux_transfer_done — struct completion used to indicate when DMUB transfers are done. ✅
• delayed_hpd_wq — work queue used to delay DMUB HPD work. ⏳
• brightness — cached backlight values. 💡
• actual_brightness — last successfully applied backlight values. 🌟
• aux_hpd_discon_quirk — quirk for hpd discon while aux is on-going. occurred on certain intel platform. 🧩
• edp0_on_dp1_quirk — quirk for platforms that put edp0 on DP1. 🧩
• dpia_aux_lock — guards access to DPIA AUX. 🔒
• bb_from_dmub — bounding box data read from dmub during early initialization for DCN4+. Data is stored as a byte array that should be casted to the appropriate bb struct. 🧱
• i2c_devres_group — devres group for DM i2c adapter lifetime management. 🧵
• oem_i2c — OEM i2c bus. 🔌
• fused_io — dmub fused io interface. 🔗
• hdmi_frl_status_polling_work — workqueue for 200ms frl status polling. ⏱️

✨ SEE ALSO ✨

okay so like, that was the whole struct, but the kernel docs are not about to let you leave without the rest of the squad 💅 these are the other kernel-doc structs that live in the same neighborhood, so go say hi:

• Kernel file ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h — this is THE header, the mothership, the one that has all of these in it 🫶
• struct dm_compressor_info(9)
• struct dm_boot_time_crc_info(9)
• struct dmub_hpd_work(9)
• struct vblank_control_work(9)
• struct idle_workqueue(9)
• struct vupdate_offload_work(9)
• struct amdgpu_dm_luminance_data(9)
• struct amdgpu_dm_backlight_caps(9)
• struct dal_allocation(9)
• struct hpd_rx_irq_offload_work_queue(9)
• struct hpd_rx_irq_offload_work(9)
• struct amdgpu_hdmi_vsdb_info(9)

like, yes, that's a lot of structs, and yes, you're gonna read them, because they're literally right there in amdgpu_dm.h and they all get their own manpages 👑 completionist behavior only, no cap.

and that's a wrap on struct amdgpu_display_manager(9) bestie 🎀 this whole page is straight out of the kernel source tree at ./drivers/gpu/drm/amd/display/... — that path is truncated in the footer but you get the vibe — and it's version-dated October 2026, title line all struct amdg...play_manager(9) because even the headers run out of room sometimes 😭 go read the code, slay, bye 💜🦋