STRUCT AIROHA_PCIE_PHY(9)

💅 struct airoha_pcie_phy(9)

okay bestie, welcome to the kernel API manual — this one's about struct airoha_pcie_phy, the main character of the PCIe phy driver. no cap, it's literally just the driver's main structure, and once you see the fields you'll be obsessed. 🌸

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✨ NAME ✨

struct airoha_pcie_phy — the PCIe phy driver main structure. that's it, that's the vibe. 👑

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🦋 SYNOPSIS 🦋

here's the whole thing, copied exactly, don't @ me:

struct airoha_pcie_phy {
    struct device *dev;
    struct phy *phy;
    void __iomem *csr_2l;
    void __iomem *pma0;
    void __iomem *pma1;
    void __iomem *p0_xr_dtime;
    void __iomem *p1_xr_dtime;
    void __iomem *rx_aeq;
 };

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🎀 Members 🎀

every field, lovingly listed, no skips:

• dev — pointer to device. the whole personality of this struct starts here. 💖
• phy — pointer to generic phy. iconic little handle. ✨
• csr_2l — Analogic lane IO mapped register base address. yes, "Analogic" with a capital A, that's how the original rolls, keep it.
• pma0 — IO mapped register base address of PMA0-PCIe.
• pma1 — IO mapped register base address of PMA1-PCIe. sibling energy fr fr.
• p0_xr_dtime — IO mapped register base address of port0 Tx-Rx detection time. port zero said main character moment. 🫶
• p1_xr_dtime — IO mapped register base address of port1 Tx-Rx detection time. port one right behind, equally slay.
• rx_aeq — IO mapped register base address of Rx AEQ training. the training arc we all needed. 🔥

ngl, lots of void __iomem * in here — every single one of those is an IO mapped register base address, so treat them with the respect they deserve. 💅

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🌈 SEE ALSO 🌈

go look at these, iykyk:

• Kernel file ./drivers/phy/phy-airoha-pcie.c
• airoha_pcie_phy_init(9)

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that's the whole page, bestie — no crumbs left behind, every field accounted for 💀✨

source: ./drivers/phy · dated October 2026 · struct airoha_pcie_phy(9) — mwah, go forth and read your registers responsibly 🧚💜