STRUCT ADRENO_SMMU_PRIV(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… struct adreno_smmu_priv(9) β€” the Kernel API Manual glow-up ✨

okay so bestie, this page is from the Kernel API Manual and it's literally the tea on struct adreno_smmu_priv, which is the private interface between adreno-smmu and the GPU. iykyk 🫢


🌸 NAME 🌸

struct adreno_smmu_priv β€” the private interface between adreno-smmu and the GPU πŸ’–


✨ SYNOPSIS ✨

here's the whole struct, copied exactly, no cap:

struct adreno_smmu_priv {
    const void *cookie;
    const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
    int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg
*cfg);
    void (*get_fault_info)(const void *cookie, struct
adreno_smmu_fault_info *info);
    void (*set_stall)(const void *cookie, bool enabled);
    void (*resume_translation)(const void *cookie, bool terminate);
    void (*set_prr_bit)(const void *cookie, bool set);
    void (*set_prr_addr)(const void *cookie, phys_addr_t page_addr);
 };

πŸŽ€ Members πŸŽ€

like, one by one, because every single one matters:

  • cookie β€” an opque token provided by adreno-smmu and passed back into the callbacks πŸͺ (yes, the original says "opque", we're keeping it, character for character, bestie)
  • get_ttbr1_cfg β€” get the TTBR1 config for the GPU's context-bank
  • set_ttbr0_cfg β€” set the TTBR0 config for the GPU's context bank. a NULL config disables TTBR0 translation, otherwise TTBR0 translation is enabled with the specified cfg πŸ”₯
  • get_fault_info β€” called by the GPU fault handler to get information about the fault 😭
  • set_stall β€” configure whether stall on fault (CFCFG) is enabled. if stalling on fault is enabled, the GPU driver must call resume_translation
  • resume_translation β€” resume translation after a fault
  • set_prr_bit β€” [optional] configure the GPU's Partially Resident Region (PRR) bit in the ACTLR register.
  • set_prr_addr β€” [optional] configure the PRR_CFG_*ADDR register with the physical address of PRR page passed from GPU driver. πŸ¦‹

πŸ’œ Description πŸ’œ

so the GPU driver (drm/msm) and adreno-smmu work together for controlling the GPU's SMMU instance. it's by necessity, fr fr β€” because the GPU is directly updating the SMMU for context switches, while on the other hand we do not want to duplicate all of the initial setup logic from arm-smmu. πŸ™ˆ

this private interface is used for the two drivers to coordinate. the cookie and callback functions are populated when the GPU driver attaches it's domain. πŸ‘‘


🌈 SEE ALSO 🌈

  • Kernel file ./include/linux/adreno-smmu-priv.h struct adreno_smmu_fault_info(9)

and that's the whole page, periodt πŸ’… this came from ./include/linux, dated October 2026, and it's struct adreno_smmu_priv(9) β€” slay, go read the header bestie πŸŽ€βœ¨

πŸ“¦ where this page comes from