STRUCT ADRENO_SMMU_PRIV(9)
π struct adreno_smmu_priv(9) β the Kernel API Manual glow-up β¨
okay so bestie, this page is from the Kernel API Manual and it's literally the tea on struct adreno_smmu_priv, which is the private interface between adreno-smmu and the GPU. iykyk π«Ά
πΈ NAME πΈ
struct adreno_smmu_priv β the private interface between adreno-smmu and the GPU π
β¨ SYNOPSIS β¨
here's the whole struct, copied exactly, no cap:
struct adreno_smmu_priv {
const void *cookie;
const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg
*cfg);
void (*get_fault_info)(const void *cookie, struct
adreno_smmu_fault_info *info);
void (*set_stall)(const void *cookie, bool enabled);
void (*resume_translation)(const void *cookie, bool terminate);
void (*set_prr_bit)(const void *cookie, bool set);
void (*set_prr_addr)(const void *cookie, phys_addr_t page_addr);
};
π Members π
like, one by one, because every single one matters:
cookieβ an opque token provided by adreno-smmu and passed back into the callbacks πͺ (yes, the original says "opque", we're keeping it, character for character, bestie)get_ttbr1_cfgβ get the TTBR1 config for the GPU's context-bankset_ttbr0_cfgβ set the TTBR0 config for the GPU's context bank. aNULLconfig disables TTBR0 translation, otherwise TTBR0 translation is enabled with the specified cfg π₯get_fault_infoβ called by the GPU fault handler to get information about the fault πset_stallβ configure whether stall on fault (CFCFG) is enabled. if stalling on fault is enabled, the GPU driver must callresume_translationresume_translationβ resume translation after a faultset_prr_bitβ [optional] configure the GPU's Partially Resident Region (PRR) bit in the ACTLR register.set_prr_addrβ [optional] configure thePRR_CFG_*ADDRregister with the physical address of PRR page passed from GPU driver. π¦
π Description π
so the GPU driver (drm/msm) and adreno-smmu work together for controlling the GPU's SMMU instance. it's by necessity, fr fr β because the GPU is directly updating the SMMU for context switches, while on the other hand we do not want to duplicate all of the initial setup logic from arm-smmu. π
this private interface is used for the two drivers to coordinate. the cookie and callback functions are populated when the GPU driver attaches it's domain. π
π SEE ALSO π
- Kernel file
./include/linux/adreno-smmu-priv.hstructadreno_smmu_fault_info(9)
and that's the whole page, periodt π
this came from ./include/linux, dated October 2026, and it's struct adreno_smmu_priv(9) β slay, go read the header bestie πβ¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms