STRUCT ADF_GEN4_TL_DEVICE_DATA_REGS(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– struct adf_gen4_tl_device_data_regs β€” a peek inside the Kernel API Manual πŸ’–

okay bestie, sit down, because we're about to get into struct adf_gen4_tl_device_data_regs and honestly? it's giving ✨telemetry era✨. This structure stores device telemetry counter values as are being populated periodically by device. that's the whole vibe β€” the device keeps topping these off like it's refilling your iced coffee πŸ§Šβ˜• and this struct is where all of it lives.


🌸 SYNOPSIS 🌸

no cap, here's the whole shape of her β€” every field, in order, exactly as she is:

struct adf_gen4_tl_device_data_regs {
    __u64 reg_tl_rd_lat_acc;
    __u64 reg_tl_gp_lat_acc;
    __u64 reg_tl_at_page_req_lat_acc;
    __u64 reg_tl_at_trans_lat_acc;
    __u64 reg_tl_re_acc;
    __u32 reg_tl_pci_trans_cnt;
    __u32 reg_tl_rd_lat_max;
    __u32 reg_tl_rd_cmpl_cnt;
    __u32 reg_tl_gp_lat_max;
    __u32 reg_tl_ae_put_cnt;
    __u32 reg_tl_bw_in;
    __u32 reg_tl_bw_out;
    __u32 reg_tl_at_page_req_cnt;
    __u32 reg_tl_at_trans_lat_cnt;
    __u32 reg_tl_at_max_tlb_used;
    __u32 reg_tl_re_cnt;
    __u32 reserved;
    struct adf_gen4_tl_slice_data_regs ath_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
    struct adf_gen4_tl_slice_data_regs cph_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
    struct adf_gen4_tl_slice_data_regs cpr_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
    struct adf_gen4_tl_slice_data_regs xlt_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
    struct adf_gen4_tl_slice_data_regs dcpr_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
    struct adf_gen4_tl_slice_data_regs pke_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
    struct adf_gen4_tl_slice_data_regs ucs_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
    struct adf_gen4_tl_slice_data_regs wat_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
    struct adf_gen4_tl_slice_data_regs wcp_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
};

like, look at her. five __u64s up top doing the heavy lifting, then it's __u32 szn πŸ”₯, one little reserved doing absolutely nothing (respect tho πŸ’…), and then nine whole slice arrays. main character energy, fr fr.


πŸŽ€ Members πŸŽ€

okay so here's the member-by-member breakdown, and no I did not skip a single one, iykyk:

  • reg_tl_rd_lat_acc β€” read latency accumulator πŸ’« (it's accumulating, she's been through a lot)
  • reg_tl_gp_lat_acc β€” get-put latency accumulator
  • reg_tl_at_page_req_lat_acc β€” AT/DevTLB page request latency accumulator
  • reg_tl_at_trans_lat_acc β€” DevTLB transaction latency accumulator
  • reg_tl_re_acc β€” accumulated ring empty time πŸ•³οΈ (the ring was empty, she kept track)
  • reg_tl_pci_trans_cnt β€” PCIe partial transactions
  • reg_tl_rd_lat_max β€” maximum logged read latency, the record-holder πŸ‘‘
  • reg_tl_rd_cmpl_cnt β€” read requests completed count βœ…
  • reg_tl_gp_lat_max β€” maximum logged get to put latency
  • reg_tl_ae_put_cnt β€” Accelerator Engine put counts across all rings, like all of them, she's thorough
  • reg_tl_bw_in β€” PCIe write bandwidth
  • reg_tl_bw_out β€” PCIe read bandwidth
  • reg_tl_at_page_req_cnt β€” DevTLB page requests count
  • reg_tl_at_trans_lat_cnt β€” DevTLB transaction latency samples count
  • reg_tl_at_max_tlb_used β€” maximum uTLB used
  • reg_tl_re_cnt β€” ring empty time samples count
  • reserved β€” reserved πŸ«₯ (she's literally just sitting there, iconic)
  • ath_slices β€” array of Authentication slices utilization registers πŸ¦‹
  • cph_slices β€” array of Cipher slices utilization registers
  • cpr_slices β€” array of Compression slices utilization registers
  • xlt_slices β€” array of Translator slices utilization registers
  • dcpr_slices β€” array of Decompression slices utilization registers
  • pke_slices β€” array of PKE slices utilization registers
  • ucs_slices β€” array of UCS slices utilization registers
  • wat_slices β€” array of Wireless Authentication slices utilization registers 🌈
  • wcp_slices β€” array of Wireless Cipher slices utilization registers
πŸ’€ reminder bestie: every single one of those slice arrays is sized ADF_GEN4_TL_MAX_SLICES_PER_TYPE. don't come for me, that's just how it is.

πŸ¦‹ SEE ALSO πŸ¦‹

go look at the Kernel file ./drivers/crypto/intel/qat/qat_common/adf_gen4_tl.h β€” and while you're in the neighborhood, say hi to struct adf_gen4_tl_slice_data_regs(9), struct adf_gen4_tl_ring_pair_data_regs(9), and struct adf_gen4_tl_layout(9) 🫢 they're all part of the same friend group, honestly.


and that's the page!! πŸŽ€ sourced from ./drivers/crypto/intel/qat/qat... and dated October 2026, brought to you by your resident kernel-obsessed bestie. slay, go read some more manpages, mwah πŸ’œβœ¨

πŸ“¦ where this page comes from