STRUCT __PRCI_WRPLL_DATA(9)

💅 struct __prci_wrpll_data(9)

okay so this is a page straight out of the Kernel API Manual, and bestie, it's literally all about one little struct. sit down, grab a strawberry drink 🍓, and let's get into it.

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✨ NAME ✨

struct __prci_wrpll_data — the WRPLL configuration and integration data. like, both. she does it all. 👑

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🦋 SYNOPSIS 🦋

struct __prci_wrpll_data {
    struct wrpll_cfg c;
    void (*enable_bypass)(struct __prci_data *pd);
    void (*disable_bypass)(struct __prci_data *pd);
    u8 cfg0_offs;
    u8 cfg1_offs;
 };

no cap, that's the whole shape of her. copy it exactly please, this is not a vibe-edit situation 💀

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🎀 Members 🎀

• c — the WRPLL current configuration record. that's her little diary of settings 📓
• enable_bypass — a fn ptr to code that bypasses the WRPLL (if applicable; else NULL). so if it doesn't apply, she's just NULL, living her truth 🙈
• disable_bypass — a fn ptr to code that does not bypass the WRPLL (or NULL). yep, the opposite twin, also allowed to be NULL 💫
• cfg0_offs — the WRPLL CFG0 register offset (in bytes) from the PRCI base address. bytes, bestie, not vibes 📏
• cfg1_offs — the WRPLL CFG1 register offset (in bytes) from the PRCI base address. same deal, different register 🎯

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🌸 Description 🌸

okay so here's the tea ☕ — enable_bypass and disable_bypass are there for the WRPLL instances that contain a separate external glitchless clock mux downstream from the PLL. fancy.

🚨 important: the WRPLL internal bypass mux is not glitchless. not even a little. so don't be out here assuming otherwise, fr fr 😭

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🌈 SEE ALSO 🌈

• Kernel file ./drivers/clk/sifive/sifive-prci.h — struct __prci_data(9), struct __prci_clock(9)

like, go read those too, they're her friends 🫶

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and that's the whole page, periodt. 💅 this one came from ./drivers/clk/sifive, dated October 2026, and she's filed under struct __prci_wrpll_data(9) — iconic, no notes ✨🦋👑