omap36xx_ga...sdiv_restore(9)

📦 version 7.3.1, in nixpkgs unstable

💅 omap36xx_ga...sdiv_restore(9) ✨

okay so this is from the Kernel API Manual bestie, and the function name is genuinely so long it got clipped 😭 — it's omap36xx_ga...sdiv_restore(9), and we're about to get into it.

🌸 NAME 🌸

omap36xx_gate_clk_enable_with_hsdiv_restore — enables clocks that are out here suffering from the HSDivider PWRDN problem 💀 and yeah, this one implements Errata ID: i556. periodt.

🦋 SYNOPSIS 🦋

int omap36xx_gate_clk_enable_with_hsdiv_restore (struct clk_hw *hw );

🎀 ARGUMENTS 🎀

  • hw — the DPLL output struct clk_hw, aka the main character we're passing in 🫶

✨ DESCRIPTION ✨

so this is 3630 only, no cap. these specific dividers:

  • dpll3_m3_ck
  • dpll4_m2_ck
  • dpll4_m3_ck
  • dpll4_m4_ck
  • dpll4_m5_ck
  • dpll4_m6_ck

they all get loaded with the reset value after their respective PWRDN bits are set 😭 like not me getting reset the second the power goes down, embarrassing.

but here's the slay: any dummy write — and by that we mean any other value different from the Read value — to the corresponding CM_CLKSEL register will refresh the dividers. so we just poke it with something else and the divider wakes up feeling iconic again 💅

ngl the whole thing is basically "read value, then write literally anything that isn't that value, and the divider gets refreshed." lowercase chaotic but it works 🧚

🔥 SEE ALSO 🔥

  • Kernel file ./drivers/clk/ti/gate.c — go read it iykyk 👑

kisses bestie, this page came to you from ./drivers/clk/ti, dated October 2026, and yeah that's the whole man page 🍓💜 stay refreshed (unlike those dividers) 🌈

📦 where this page comes from