nvkm_gsp_radix3_sg(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… nvkm_gsp_radix3_sg β€” like, the kernel API manual one

okay so bestie, welcome to nvkm_gsp_radix3_sg(9) πŸ’– this is the page where we build a radix3 table out of a scatter/gather list, and honestly? it's giving main character energy. stay with me, i promise it slaps.


✨ NAME ✨

nvkm_gsp_radix3_sg β€” build a radix3 table from a S/G list πŸŽ€


🌸 SYNOPSIS 🌸

int nvkm_gsp_radix3_sg (struct nvkm_gsp *gsp , struct sg_table *sgt ,
u64 size , struct nvkm_gsp_radix3 *rx3 );

like, that's the whole vibe check right there, no cap ✨


πŸ¦‹ ARGUMENTS πŸ¦‹

  • gsp β€” the gsp pointer 🫢 that's it, that's the descriptor
  • sgt β€” the S/G list we're gonna traverse, walk it like a runway πŸ’…
  • size β€” how big the image is, in bytes. yes, actual bytes
  • rx3 β€” the radix3 array we're updating. bestie is getting a glow-up in place ✨

πŸ‘‘ DESCRIPTION πŸ‘‘

okay so the GSP uses a three-level page table, and it's literally called radix3, and its whole job is mapping the firmware πŸ”₯ each 64-bit "pointer" in the table is one of two things, and you gotta know which:

  • the bus address of an entry in the next table β€” that's for levels 0 and 1
  • the bus address of the next page in the GSP firmware image itself

πŸ’œ Level 0

level 0 contains a single entry, in one page, that points to the first page of level 1. one entry. iconic minimalism πŸŽ€

πŸ’œ Level 1

level 1, since it's also only one page in size, contains up to 512 entries, one for each page in level 2. slay, a whole 512 of them.

πŸ’œ Level 2

level 2 can be up to 512 pages in size, and each of those entries points to the next page of the firmware image. and since there can be up to 512*512 pages, that caps the firmware at:

512*512*GSP_PAGE_SIZE = 1GB

that's the ceiling, bestie. 1GB. no notes. πŸ’€

🧚 the whole memory situation

internally, the GSP has its window into system memory, but the base physical address of the aperture is not 0 β€” like, at all. in fact, it varies depending on the GPU architecture πŸ™ˆ and since the GPU is a PCI device, this window is accessed via DMA, so it's bound by IOMMU translation. the end result? GSP-RM must translate the bus addresses in the table into GSP physical addresses. all of this should happen transparently, so don't stress about it 🌈

⭐ returns

returns 0 on success, or a negative error code 😭 (we love a clear signal)

also, see kgspCreateRadix3_IMPL β€” that's the reference, iykyk πŸ‘‘

πŸ“ SEE ALSO πŸ“

the kernel file, first and foremost:

./drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

and then the whole friend group, fr fr:


πŸ’– and that's the page!! this one came out of ./drivers/gpu/drm/nouveau/nvkm... and it's dated October 2026, so mark your calendars bestie πŸ—“οΈβœ¨ stay hydrated, read your page tables, and remember: 512*512*GSP_PAGE_SIZE = 1GB. periodt. πŸ’…πŸ«Ά

πŸ“¦ where this page comes from