igb_write_p..._sgmii_82575(9)
Okay bestie, this is the igb_write_p..._sgmii_82575(9) page from the Kernel API Manual, and it's literally about writing a PHY register using sgmii. No cap, the vibe is very "hardware girlie who knows her registers" π
β¨
π NAME π
igb_write_phy_reg_sgmii_82575 β write PHY register using sgmii. That's the whole name, periodt π«Ά
β¨ SYNOPSIS β¨
s32 igb_write_phy_reg_sgmii_82575 (struct e1000_hw *hw , u32 offset ,
u16 data );
π«Ά ARGUMENTS π«Ά
hwβ pointer to the HW structure, the main character we're working on π«Άoffsetβ register offset to write to, aka where the data goes πdataβ data to write at register offset, fr fr
π¦ DESCRIPTION π¦
So this function writes the data to the PHY register at the offset using the serial gigabit media independent interface. That's the whole slay, lowkey iconic β¨
π SEE ALSO π
Kernel file: ./drivers/net/ethernet/intel/igb/e1000_82575.c β the source file this page points to π«Ά
igb_write_vfta_i350(9)igb_sgmii_uses_mdio_82575(9)igb_check_for_link_media_swap(9)igb_init_phy_params_82575(9)igb_init_nvm_params_82575(9)igb_init_mac_params_82575(9)igb_set_sfp_media_type_82575(9)igb_acquire_phy_82575(9)igb_release_phy_82575(9)igb_read_phy_reg_sgmii_82575(9)igb_get_phy_id_82575(9)igb_phy_hw_reset_sgmii_82575(9)igb_set_d0_lplu_state_82575(9)igb_set_d0_lplu_state_82580(9)igb_set_d3_lplu_state_82580(9)igb_acquire_nvm_82575(9)igb_release_nvm_82575(9)igb_acquire_swfw_sync_82575(9)igb_release_swfw_sync_82575(9)igb_get_cfg_done_82575(9)igb_get_link_up_info_82575(9)igb_check_for_link_82575(9)igb_power_up_serdes_link_82575(9)igb_get_pcs_speed_and_duplex_82575(9)igb_shutdown_serdes_link_82575(9)igb_reset_hw_82575(9)igb_init_hw_82575(9)igb_setup_copper_link_82575(9)igb_setup_serdes_link_82575(9)igb_sgmii_active_82575(9)igb_reset_init_script_82575(9)igb_read_mac_addr_82575(9)igb_power_down_phy_copper_82575(9)igb_clear_hw_cntrs_82575(9)igb_rx_fifo_flush_82575(9)igb_set_pcie_completion_timeout(9)igb_vmdq_set_anti_spoofing_pf(9)igb_vmdq_set_loopback_pf(9)igb_vmdq_set_replication_pf(9)igb_read_phy_reg_82580(9)igb_write_phy_reg_82580(9)igb_reset_mdicnfg_82580(9)igb_reset_hw_82580(9)igb_rxpbs_adjust_82580(9)igb_validate_nvm_checksum_with_offset(9)igb_update_nvm_checksum_with_offset(9)igb_validate_nvm_checksum_82580(9)igb_update_nvm_checksum_82580(9)igb_validate_nvm_checksum_i350(9)igb_update_nvm_checksum_i350(9)__igb_access_emi_reg(9)igb_read_emi_reg(9)igb_set_eee_i350(9)igb_set_eee_i354(9)igb_get_eee_status_i354(9)igb_get_thermal_sensor_data_generic(9)igb_init_thermal_sensor_thresh_generic(9)
Cute sign-off: this whole page comes from./drivers/net/ethernet/intel/igb, dated October 2026, and it's theigb_write_p..._sgmii_82575(9)page from the Kernel API Manual. Bye bestie, go write that PHY register π πβ¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms