hpt3x2n_set_clock(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… hpt3x2n_set_clock β€” clock control (kernel API manual, bestie edition)

okay so this is a kernel API manual page, and the function we're obsessing over is hpt3x2n_set_clock. she's a clock-control girly. that's the whole vibe. let's get into it ✨


🌸 SYNOPSIS 🌸

void hpt3x2n_set_clock (struct ata_port *ap , int source );

like, that's the whole signature. no return value, she's a void, she just does things and leaves. main character energy fr πŸ’…


πŸŽ€ ARGUMENTS πŸŽ€

  • ap β€” the ATA port. that's your girl, the thing we're clocking. πŸ¦‹
  • source β€” the clock source you're picking, and it's gotta be 0x21 or 0x23 for a PLL or PCI sourced clock respectively. no other numbers, bestie, those are the two options periodt.

⭐ DESCRIPTION ⭐

so what she actually does: she switches the ATA bus clock back and forth between the PLL and the PCI clock sources β€” and the important part, the part that makes her iconic, is that she does it while correctly isolating the bus and resetting internal logic. like she doesn't just yank the clock out from under everything, she's careful. she's considerate. she's a professional. πŸ‘‘

now here's the tea you actually need to remember: we must use the DPLL for these three situations, no exceptions:

  • writing πŸ“
  • second channel UDMA7 (SATA ports) or higher ⚑
  • 66MHz PCI πŸ”₯
and if you don't? you will underclock the device and get reduced performance. that's the warning, that's the consequence, i don't make the rules. do not skip the DPLL. i'm literally begging. 😭

πŸ‘‘ SEE ALSO πŸ‘‘

the kernel file this all lives in is ./drivers/ata/pata_hpt3x2n.c, and honestly the whole friend group shows up here:

go read them, they're all slay too 🫢✨


okay that's the page!! this one's from ./drivers/ata, dated October 2026, and it's part of the Kernel API Manual β€” so like, shoutout to the kernel docs era, we're living in it. bye bestie, go set some clocks responsibly πŸ’–πŸŽ€πŸ¦‹

πŸ“¦ where this page comes from