ENUM RISCV_IOMMU_IGS_SETTINGS(9)

💖 ENUM RISCV_IOMMU_IGS_SETTINGS 💖

okay so bestie, welcome to the Kernel API Manual ✨ this one's a lil baby page but she's important, she's literally the enum riscv_iommu_igs_settings and she's here to tell you how the RISC-V IOMMU is allowed to generate interrupts. Interrupt Generation Support Settings, iykyk 🎀

This is the interrupt-generation vibe check: the IOMMU can poke you with MSI, or with Wired-Signaled interrupts, or honestly both, or it can be the mysterious reserved one 👀

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✨ NAME ✨

enum riscv_iommu_igs_settings — Interrupt Generation Support Settings. that's the whole name, that's the whole job 🫶

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🌸 SYNOPSIS 🌸

enum riscv_iommu_igs_settings {
    RISCV_IOMMU_CAPABILITIES_IGS_MSI ,
    RISCV_IOMMU_CAPABILITIES_IGS_WSI ,
    RISCV_IOMMU_CAPABILITIES_IGS_BOTH ,
    RISCV_IOMMU_CAPABILITIES_IGS_RSRV

};

like, four members, all caps, all iconic 👑

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💅 CONSTANTS 💅

so here's the lineup — one bullet per member, no skipping, that's the rule fr fr:

• RISCV_IOMMU_CAPABILITIES_IGS_MSI — the IOMMU supports only MSI generation. MSI girlies only, no WSI, periodt 💫
• RISCV_IOMMU_CAPABILITIES_IGS_WSI — the IOMMU supports only Wired-Signaled interrupt. wired-signaled supremacy, nothing else 😌
• RISCV_IOMMU_CAPABILITIES_IGS_BOTH — the IOMMU supports both MSI and WSI generation. she's flexible, she's multi-talented, main character energy 🔥
• RISCV_IOMMU_CAPABILITIES_IGS_RSRV — Reserved for standard use. not for you, bestie, hands off 🙈

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🦋 SEE ALSO 🦋

okay this is the friend group, they all live together:

• Kernel file ./drivers/iommu/riscv/iommu-bits.h enum — that's where she lives, that's her house 🏠
• riscv_iommu_ddtp_modes(9)
• enum riscv_iommu_hpmevent_id(9)
• struct riscv_iommu_dc(9)
• enum riscv_iommu_dc_iohgatp_modes(9)
• enum riscv_iommu_dc_fsc_atp_modes(9)
• struct riscv_iommu_pc(9)
• struct riscv_iommu_command(9)
• struct riscv_iommu_fq_record(9)
• enum riscv_iommu_fq_causes(9)
• enum riscv_iommu_fq_ttypes(9)
• struct riscv_iommu_pq_record(9)
• struct riscv_iommu_msipte(9)

ngl the RISC-V IOMMU corner of the kernel is a whole friend group and this enum is just one of them — go read the rest, they all link up 🧚

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✨ cute sign-off ✨

this gorgeous little page came out of ./drivers/iommu/riscv, dated October 2026, and the manual is the Kernel API Manual. slay, bye, go interrupt something 💜🌸