ENUM RISCV_IOMMU_HPMEVENT_ID(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

✨ NAME ✨

enum riscv_iommu_hpmevent_id β€” the performance-monitoring event identifier, bestie πŸ’…

Ok so real talk, this is the enum that tells the RISC-V IOMMU which performance event you're counting. Every counter you point at one of these and it's like "okay girl, I'll track that for you" ✨


🌸 SYNOPSIS 🌸

enum riscv_iommu_hpmevent_id {
    RISCV_IOMMU_HPMEVENT_INVALID ,
    RISCV_IOMMU_HPMEVENT_URQ ,
    RISCV_IOMMU_HPMEVENT_TRQ ,
    RISCV_IOMMU_HPMEVENT_ATS_RQ ,
    RISCV_IOMMU_HPMEVENT_TLB_MISS ,
    RISCV_IOMMU_HPMEVENT_DD_WALK ,
    RISCV_IOMMU_HPMEVENT_PD_WALK ,
    RISCV_IOMMU_HPMEVENT_S_VS_WALKS ,
    RISCV_IOMMU_HPMEVENT_G_WALKS ,
    RISCV_IOMMU_HPMEVENT_MAX

};

πŸ’– Constants πŸ’–

Like, here's the whole roster, no gatekeeping 🫢

  • RISCV_IOMMU_HPMEVENT_INVALID β€” the "nah, don't count anything" event. Invalid, literally do not count, it's giving placeholder energy πŸ™ˆ
  • RISCV_IOMMU_HPMEVENT_URQ β€” untranslated requests πŸ‘‘
  • RISCV_IOMMU_HPMEVENT_TRQ β€” translated requests πŸ’«
  • RISCV_IOMMU_HPMEVENT_ATS_RQ β€” ATS translation requests πŸ¦‹
  • RISCV_IOMMU_HPMEVENT_TLB_MISS β€” TLB misses 😭 (and yeah, there will be a lot of them)
  • RISCV_IOMMU_HPMEVENT_DD_WALK β€” device directory walks πŸšΆβ€β™€οΈ
  • RISCV_IOMMU_HPMEVENT_PD_WALK β€” process directory walks πŸšΆβ€β™€οΈπŸšΆβ€β™€οΈ
  • RISCV_IOMMU_HPMEVENT_S_VS_WALKS β€” first-stage page table walks, our main character ✨
  • RISCV_IOMMU_HPMEVENT_G_WALKS β€” second-stage page table walks, the sequel 🎬
  • RISCV_IOMMU_HPMEVENT_MAX β€” the sentinel value that denotes the maximum Event IDs, iykyk πŸŽ€

πŸ¦‹ SEE ALSO πŸ¦‹

Kernel file ./drivers/iommu/riscv/iommu-bits.h ⭐ and the whole enum friend group, fr fr:

enum riscv_iommu_igs_settings(9), enum riscv_iommu_ddtp_modes(9), struct riscv_iommu_dc(9), enum riscv_iommu_dc_iohgatp_modes(9), enum riscv_iommu_dc_fsc_atp_modes(9), struct riscv_iommu_pc(9), struct riscv_iommu_command(9), struct riscv_iommu_fq_record(9), enum riscv_iommu_fq_causes(9), enum riscv_iommu_fq_ttypes(9), struct riscv_iommu_pq_record(9), struct riscv_iommu_msipte(9)


Lowkey obsessed with this one, ngl. Go read the whole squad πŸ’œ

That's the whole vibe check, bestie 🧚 this came from ./drivers/iommu/riscv, dated October 2026, and it's the enum riscv_i..._hpmevent_id(9) page β€” slay, go count some events πŸ’…πŸŒΈ

πŸ“¦ where this page comes from