ENUM RISCV_IOMMU_FQ_TTYPES(9)

💅 enum riscv_iommu_fq_ttypes(9) — Fault/event transaction types

okay so bestie, welcome to the Kernel API Manual ✨ this one's a little enum from the RISC-V IOMMU corner of the kernel, and honestly? it's giving "labels for why your transaction got cancelled" 🎀 let's get into it.

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✨ NAME ✨

enum riscv_iommu_fq_ttypes — Fault/event transaction types 💖

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🌸 SYNOPSIS 🌸

enum riscv_iommu_fq_ttypes {
    RISCV_IOMMU_FQ_TTYP_NONE ,
    RISCV_IOMMU_FQ_TTYP_UADDR_INST_FETCH ,
    RISCV_IOMMU_FQ_TTYP_UADDR_RD ,
    RISCV_IOMMU_FQ_TTYP_UADDR_WR ,
    RISCV_IOMMU_FQ_TTYP_TADDR_INST_FETCH ,
    RISCV_IOMMU_FQ_TTYP_TADDR_RD ,
    RISCV_IOMMU_FQ_TTYP_TADDR_WR ,
    RISCV_IOMMU_FQ_TTYP_PCIE_ATS_REQ ,
    RISCV_IOMMU_FQ_TTYP_PCIE_MSG_REQ

};

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🦋 Constants 🦋

bestie these are the members, one by one, no skips, we love a complete list 👑

• RISCV_IOMMU_FQ_TTYP_NONE — None, periodt. This fault was not caused by an inbound transaction 🙈
• RISCV_IOMMU_FQ_TTYP_UADDR_INST_FETCH — Instruction fetch from an untranslated address 🌈
• RISCV_IOMMU_FQ_TTYP_UADDR_RD — Read from an untranslated address 📖
• RISCV_IOMMU_FQ_TTYP_UADDR_WR — Write/AMO to an untranslated address ✍️
• RISCV_IOMMU_FQ_TTYP_TADDR_INST_FETCH — Instruction fetch from a translated address 🧚
• RISCV_IOMMU_FQ_TTYP_TADDR_RD — Read from a translated address 💜
• RISCV_IOMMU_FQ_TTYP_TADDR_WR — Write/AMO to a translated address 🔥
• RISCV_IOMMU_FQ_TTYP_PCIE_ATS_REQ — PCIe ATS translation request ⭐
• RISCV_IOMMU_FQ_TTYP_PCIE_MSG_REQ — PCIe message request 💌

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🎀 Description 🎀

so these values live on table 12 of the spec — iconic behavior ngl. heads up tho: type 4 and 10 - 31 are reserved for standard use, and 31 - 63 for custom use 🫶

lowkey important: those reserved ranges are exactly as written in the spec, so don't go inventing your own numbers in there, bestie 😭

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💀 SEE ALSO 💀

the kernel file is ./drivers/iommu/riscv/iommu-bits.h — that's the enum's home, go say hi 🌸

and the whole friend group 🫶: enum riscv_iommu_igs_settings(9), enum riscv_iommu_ddtp_modes(9), enum riscv_iommu_hpmevent_id(9), struct riscv_iommu_dc(9), enum riscv_iommu_dc_iohgatp_modes(9), enum riscv_iommu_dc_fsc_atp_modes(9), struct riscv_iommu_pc(9), struct riscv_iommu_command(9), struct riscv_iommu_fq_record(9), enum riscv_iommu_fq_causes(9), struct riscv_iommu_pq_record(9), struct riscv_iommu_msipte(9)

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and that's the page, mwah 💋 this lil cutie came from ./drivers/iommu/riscv, dated October 2026, and it's filed under enum riscv_iommu_fq_ttypes(9) — go read the other ones too, iykyk 💅✨