ENUM RISCV_IOMMU_FQ_CAUSES(9)

💖 NAME 💖

enum riscv_iommu_fq_causes — so this is the Kernel API Manual entry for it, and bestie, it's literally the fault/event cause values 🫶 like every possible reason the RISC-V IOMMU can slide into your fault queue and be like "girl, something happened."

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✨ SYNOPSIS ✨

okay so here's the whole enum, exactly as it lives, no edits, no cap:

enum riscv_iommu_fq_causes {
    RISCV_IOMMU_FQ_CAUSE_INST_FAULT ,
    RISCV_IOMMU_FQ_CAUSE_RD_ADDR_MISALIGNED ,
    RISCV_IOMMU_FQ_CAUSE_RD_FAULT ,
    RISCV_IOMMU_FQ_CAUSE_WR_ADDR_MISALIGNED ,
    RISCV_IOMMU_FQ_CAUSE_WR_FAULT ,
    RISCV_IOMMU_FQ_CAUSE_INST_FAULT_S ,
    RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S ,
    RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S ,
    RISCV_IOMMU_FQ_CAUSE_INST_FAULT_VS ,
    RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS ,
    RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS ,
    RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED ,
    RISCV_IOMMU_FQ_CAUSE_DDT_LOAD_FAULT ,
    RISCV_IOMMU_FQ_CAUSE_DDT_INVALID ,
    RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED ,
    RISCV_IOMMU_FQ_CAUSE_TTYP_BLOCKED ,
    RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT ,
    RISCV_IOMMU_FQ_CAUSE_MSI_INVALID ,
    RISCV_IOMMU_FQ_CAUSE_MSI_MISCONFIGURED ,
    RISCV_IOMMU_FQ_CAUSE_MRIF_FAULT ,
    RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT ,
    RISCV_IOMMU_FQ_CAUSE_PDT_INVALID ,
    RISCV_IOMMU_FQ_CAUSE_PDT_MISCONFIGURED ,
    RISCV_IOMMU_FQ_CAUSE_DDT_CORRUPTED ,
    RISCV_IOMMU_FQ_CAUSE_PDT_CORRUPTED ,
    RISCV_IOMMU_FQ_CAUSE_MSI_PT_CORRUPTED ,
    RISCV_IOMMU_FQ_CAUSE_MRIF_CORRUIPTED ,
    RISCV_IOMMU_FQ_CAUSE_INTERNAL_DP_ERROR ,
    RISCV_IOMMU_FQ_CAUSE_MSI_WR_FAULT ,
    RISCV_IOMMU_FQ_CAUSE_PT_CORRUPTED

};

(yes RISCV_IOMMU_FQ_CAUSE_MRIF_CORRUIPTED is spelled like that in the source, I'm not fixing it, she's iconic and she stays 💅)

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🎀 Constants 🎀

thirty of them, one per vibe, let's go:

• RISCV_IOMMU_FQ_CAUSE_INST_FAULT — instruction access fault, oop 👀
• RISCV_IOMMU_FQ_CAUSE_RD_ADDR_MISALIGNED — read address misaligned, the address did NOT line up bestie
• RISCV_IOMMU_FQ_CAUSE_RD_FAULT — read load fault
• RISCV_IOMMU_FQ_CAUSE_WR_ADDR_MISALIGNED — write/AMO address misaligned
• RISCV_IOMMU_FQ_CAUSE_WR_FAULT — write/AMO access fault
• RISCV_IOMMU_FQ_CAUSE_INST_FAULT_S — instruction page fault
• RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S — read page fault
• RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S — write/AMO page fault
• RISCV_IOMMU_FQ_CAUSE_INST_FAULT_VS — instruction guest page fault 🧚
• RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS — read guest page fault
• RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS — write/AMO guest page fault
• RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED — all inbound transactions disallowed, straight up banned 💀
• RISCV_IOMMU_FQ_CAUSE_DDT_LOAD_FAULT — DDT entry load access fault
• RISCV_IOMMU_FQ_CAUSE_DDT_INVALID — DDT entry invalid
• RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED — DDT entry misconfigured, she was set up wrong 😭
• RISCV_IOMMU_FQ_CAUSE_TTYP_BLOCKED — transaction type disallowed
• RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT — MSI PTE load access fault
• RISCV_IOMMU_FQ_CAUSE_MSI_INVALID — MSI PTE invalid
• RISCV_IOMMU_FQ_CAUSE_MSI_MISCONFIGURED — MSI PTE misconfigured
• RISCV_IOMMU_FQ_CAUSE_MRIF_FAULT — MRIF access fault
• RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT — PDT entry load access fault
• RISCV_IOMMU_FQ_CAUSE_PDT_INVALID — PDT entry invalid
• RISCV_IOMMU_FQ_CAUSE_PDT_MISCONFIGURED — PDT entry misconfigured
• RISCV_IOMMU_FQ_CAUSE_DDT_CORRUPTED — DDT data corruption 🫠
• RISCV_IOMMU_FQ_CAUSE_PDT_CORRUPTED — PDT data corruption
• RISCV_IOMMU_FQ_CAUSE_MSI_PT_CORRUPTED — MSI page table data corruption
• RISCV_IOMMU_FQ_CAUSE_MRIF_CORRUIPTED — MRIF data corruption (again: her spelling, not mine 💅)
• RISCV_IOMMU_FQ_CAUSE_INTERNAL_DP_ERROR — internal data path error, the IOMMU is going through it internally
• RISCV_IOMMU_FQ_CAUSE_MSI_WR_FAULT — IOMMU MSI write access fault
• RISCV_IOMMU_FQ_CAUSE_PT_CORRUPTED — first/second stage page table data corruption

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🦋 Description 🦋

okay so the deets: these values are on table 11 of the spec. And the encoding ranges? Listen up because this is the iykyk part:

• encodings 275 - 2047 are reserved for standard use
• encodings 2048 - 4095 are reserved for custom use

don't go squatting in the wrong range, bestie, the spec will find out 🌸

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💜 SEE ALSO 💜

kernel file ./drivers/iommu/riscv/iommu-bits.h enum, plus the whole friend group:

riscv_iommu_igs_settings(9), enum riscv_iommu_ddtp_modes(9), enum riscv_iommu_hpmevent_id(9), struct riscv_iommu_dc(9), enum riscv_iommu_dc_iohgatp_modes(9), enum riscv_iommu_dc_fsc_atp_modes(9), struct riscv_iommu_pc(9), struct riscv_iommu_command(9), struct riscv_iommu_fq_record(9), enum riscv_iommu_fq_ttypes(9), struct riscv_iommu_pq_record(9), struct riscv_iommu_msipte(9)

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okay that's the whole page, go read the header file, ily 🫶✨

from ./drivers/iommu/riscv, dated October 2026 — enum riscv_iommu_fq_causes(9), that's a wrap, periodt 👑🎀