ENUM RISCV_IOMMU_DDTP_MODES(9)

✨ enum riscv_iommu_ddtp_modes(9) ✨

okay bestie, welcome to the manpage for enum riscv_iommu_ddtp_modes(9) — that's the kernel API doc for this little enum that tells the RISC-V IOMMU how it should be translating stuff. It's giving "translation mode selector" energy and honestly it ate 💅

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🎀 NAME 🎀

enum riscv_iommu_ddtp_modes — IOMMU translation modes. that's literally it. the vibes menu for how your IOMMU does its thing ✨

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🦋 SYNOPSIS 🦋

here's the shape of the whole enum, copied exactly so you can trust me fr fr:

enum riscv_iommu_ddtp_modes {
    RISCV_IOMMU_DDTP_IOMMU_MODE_OFF ,
    RISCV_IOMMU_DDTP_IOMMU_MODE_BARE ,
    RISCV_IOMMU_DDTP_IOMMU_MODE_1LVL ,
    RISCV_IOMMU_DDTP_IOMMU_MODE_2LVL ,
    RISCV_IOMMU_DDTP_IOMMU_MODE_3LVL ,
    RISCV_IOMMU_DDTP_IOMMU_MODE_MAX

};

like, look at her. six constants. main character lineup 🌈

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💖 Constants 💖

okay so let's do a vibe check on each one, in order, no skipping (i would never 🙈):

• RISCV_IOMMU_DDTP_IOMMU_MODE_OFF — no inbound transactions allowed. that's it, doors closed, we're not accepting visitors 😭
• RISCV_IOMMU_DDTP_IOMMU_MODE_BARE — pass-through mode. no translation, just vibes, come on through 🫶
• RISCV_IOMMU_DDTP_IOMMU_MODE_1LVL — one-level DDT. single layer, lowkey simple ✨
• RISCV_IOMMU_DDTP_IOMMU_MODE_2LVL — two-level DDT. now we're stacking 🎀
• RISCV_IOMMU_DDTP_IOMMU_MODE_3LVL — three-level DDT. three layers, highkey extra 💅
• RISCV_IOMMU_DDTP_IOMMU_MODE_MAX — the max value allowed by specification. the ceiling, the limit, the final boss 👑

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👑 SEE ALSO 👑

bestie, there is SO much more lore where this came from. the kernel file is ./drivers/iommu/riscv/iommu-bits.h (that's the enum source, iykyk) and you're gonna want to go read these next:

• enum riscv_iommu_igs_settings(9)
• enum riscv_iommu_hpmevent_id(9)
• struct riscv_iommu_dc(9)
• enum riscv_iommu_dc_iohgatp_modes(9)
• enum riscv_iommu_dc_fsc_atp_modes(9)
• struct riscv_iommu_pc(9)
• struct riscv_iommu_command(9)
• struct riscv_iommu_fq_record(9)
• enum riscv_iommu_fq_causes(9)
• enum riscv_iommu_fq_ttypes(9)
• struct riscv_iommu_pq_record(9)
• struct riscv_iommu_msipte(9)

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ngl, this page is short but it's iconic. six modes, one enum, zero notes. periodt 💜

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and that's the whole thing, bestie — big slay, no cap 🌸

signing off from ./drivers/iommu/riscv, dated October 2026, brought to you by the enum riscv_iommu_ddtp_modes(9) manual page 🎀✨🦋