ENUM RISCV_IOMMU_DC_IOHGATP_MODES(9)

💅 enum riscv_iommu_dc_iohgatp_modes(9) 💅

okay so bestie, we're in the Kernel API Manual and this page is literally about the guest address translation/protection modes — the enum enum riscv_iommu_dc_iohgatp_modes, no cap 🎀

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🌸 NAME 🌸

enum riscv_iommu_dc_iohgatp_modes — guest address translation/protection modes, and yes that's the whole vibe 🦋

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✨ SYNOPSIS ✨

here's the whole squad, look at them:

enum riscv_iommu_dc_iohgatp_modes {
    RISCV_IOMMU_DC_IOHGATP_MODE_BARE ,
    RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4 ,
    RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4 ,
    RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4 ,
    RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4

};

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👑 Constants 👑

bestie these are the constants, one by one, let me introduce you 💖

• RISCV_IOMMU_DC_IOHGATP_MODE_BARE — no translation/protection. that's it, that's the mode. nothing happening, zero drama, we love a minimalist 🙈
• RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4 — Sv32x4 (the 2-bit extension of Sv32), and it kicks in when fctl.GXL == 1. clock that condition, it matters 🔥
• RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4 — Sv39x4 (2-bit extension of Sv39), when fctl.GXL == 0. note the 0, not a 1, okurrr ⭐
• RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4 — Sv48x4 (2-bit extension of Sv48), when fctl.GXL == 0. same condition, bigger numbers, iconic behavior 💅
• RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4 — Sv57x4 (2-bit extension of Sv57), when fctl.GXL == 0. the biggest one, main character energy, still fctl.GXL == 0 though 🧚

ngl bestie the fctl.GXL condition is doing a LOT of work here — 1 means Sv32x4, 0 means the rest. don't mix that up or it's giving "undefined chaos" 😭

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🦋 SEE ALSO 🦋

go read these next, they're all in the same friend group 💜

• Kernel file ./drivers/iommu/riscv/iommu-bits.h enum riscv_iommu_igs_settings(9)
• enum riscv_iommu_ddtp_modes(9)
• enum riscv_iommu_hpmevent_id(9)
• struct riscv_iommu_dc(9)
• enum riscv_iommu_dc_fsc_atp_modes(9)
• struct riscv_iommu_pc(9)
• struct riscv_iommu_command(9)
• struct riscv_iommu_fq_record(9)
• enum riscv_iommu_fq_causes(9)
• enum riscv_iommu_fq_ttypes(9)
• struct riscv_iommu_pq_record(9)
• struct riscv_iommu_msipte(9)

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okay that's the whole page bestie, you ate that 💖 this one lives in ./drivers/iommu/riscv, dated October 2026, and it's filed under enum riscv_...ohgatp_modes(9) — mwah, go slay some address translation 🌈🎀