ENUM RISCV_IOMMU_DC_FSC_ATP_MODES(9)

✨ enum riscv_iommu_dc_fsc_atp_modes ✨

okay so bestie, welcome to the Kernel API Manual 💖 — this little page is all about enum riscv_iommu_dc_fsc_atp_modes, aka First stage address translation/protection modes. yes it's a mouthful, no you don't have to say it out loud. 🎀

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🌸 NAME 🌸

enum riscv_iommu_dc_fsc_atp_modes — First stage address translation/protection modes 🦋

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⭐ SYNOPSIS ⭐

here's the whole squad, literally all of them, exactly as declared:

enum riscv_iommu_dc_fsc_atp_modes {
    RISCV_IOMMU_DC_FSC_MODE_BARE ,
    RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 ,
    RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39 ,
    RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48 ,
    RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57 ,
    RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8 ,
    RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17 ,
    RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20

};

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🎀 Constants 🎀

okay let's meet the members, one by one, no skipping, we love a complete list 👑

• RISCV_IOMMU_DC_FSC_MODE_BARE — No translation/protection. the "vibes only, no rules" setting 🕊️
• RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 — Sv32, when dc.tc.SXL == 1
• RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39 — Sv39, when dc.tc.SXL == 0
• RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48 — Sv48, when dc.tc.SXL == 0
• RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57 — Sv57, when dc.tc.SXL == 0
• RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8 — 1lvl PDT, 8bit process ids 🍓
• RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17 — 2lvl PDT, 17bit process ids 🌈
• RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20 — 3lvl PDT, 20bit process ids 💜

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🦋 Description 🦋

so like, here's the tea ☕ — FSC holds IOSATP when RISCV_IOMMU_DC_TC_PDTV is 0, and holds PDTP otherwise. iykyk.

IOSATP controls the first stage address translation (same as the satp register on the RISC-V MMU, bestie — literally the same energy). and PDTP holds the process directory table, which is used to select a first stage page table based on a process id — for devices that support multiple process ids 👀✨

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💅 SEE ALSO 💅

go read these next, they're lowkey iconic:

• Kernel file ./drivers/iommu/riscv/iommu-bits.h enum
• riscv_iommu_igs_settings(9), enum riscv_iommu_ddtp_modes(9), enum riscv_iommu_hpmevent_id(9), struct riscv_iommu_dc(9), enum riscv_iommu_dc_iohgatp_modes(9), struct riscv_iommu_pc(9), struct riscv_iommu_command(9), struct riscv_iommu_fq_record(9), enum riscv_iommu_fq_causes(9), enum riscv_iommu_fq_ttypes(9), struct riscv_iommu_pq_record(9), struct riscv_iommu_msipte(9)

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and that's the whole page, bestie 🫶 this came from ./drivers/iommu/riscv, dated October 2026, and it's all about enum riscv_...sc_atp_modes(9) — slay, go forth and translate your first stage addresses responsibly 💖✨