ENUM MTK_HDMI_DDC_V2_CMDS(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… enum mtk_hdmi_ddc_v2_cmds(9) πŸ’…

okay bestie, welcome to the Kernel API Manual β€” yes that's the manual name, and yes this page is a whole ~serve~. we're talking about a little enum that holds all the DDC_CMD register commands for the MediaTek HDMI DDC v2 situation. it's giving "small header file, big responsibilities" and honestly? obsessed. πŸŽ€


✨ NAME ✨

enum mtk_hdmi_ddc_v2_cmds β€” the DDC_CMD register commands, all lined up like they're waiting for the group photo πŸ“Έ


πŸ¦‹ SYNOPSIS πŸ¦‹

enum mtk_hdmi_ddc_v2_cmds {
    DDC_CMD_READ_NOACK ,
    DDC_CMD_READ ,
    DDC_CMD_SEQ_READ_NOACK ,
    DDC_CMD_SEQ_READ ,
    DDC_CMD_ENH_READ_NOACK ,
    DDC_CMD_ENH_READ ,
    DDC_CMD_SEQ_WRITE_NOACK ,
    DDC_CMD_SEQ_WRITE ,
    DDC_CMD_CLEAR_FIFO ,
    DDC_CMD_CLOCK_SCL ,
    DDC_CMD_ABORT_XFER

};

like. look at that list. eleven constants, zero filler, all main character energy πŸ‘‘


🌈 Constants 🌈

okay so here's the roll call, and yes i'm gonna introduce each one because they all deserve it 🫢

  • DDC_CMD_READ_NOACK β€” current address read, but with no ACK on the last byte. she simply does not acknowledge. πŸ’…
  • DDC_CMD_READ β€” current address read, and this one does ACK on the last byte. polite. well-mannered. we love her. ✨
  • DDC_CMD_SEQ_READ_NOACK β€” sequential read, going full no-ACK on the last byte 😭
  • DDC_CMD_SEQ_READ β€” sequential read, ACK on the last byte, thriving, hydrated 🧚
  • DDC_CMD_ENH_READ_NOACK β€” enhanced read, no ACK on the last byte. enhanced in what way? the manpage doesn't say and honestly i respect the mystery πŸ™ˆ
  • DDC_CMD_ENH_READ β€” enhanced read, ACK on the last byte, a true icon πŸ”₯
  • DDC_CMD_SEQ_WRITE_NOACK β€” sequential write that straight-up ignores the ACK on the last byte. bold. reckless? maybe. iconic? absolutely. πŸ’€
  • DDC_CMD_SEQ_WRITE β€” sequential write that requires an ACK on the last byte. she has standards. periodt. πŸ‘‘
  • DDC_CMD_CLEAR_FIFO β€” clears the DDC I2C FIFO. fresh start, clean slate, new me energy 🧹
  • DDC_CMD_CLOCK_SCL β€” starts clocking the DDC I2C SCL. get it moving, get it going ⏰
  • DDC_CMD_ABORT_XFER β€” aborts the DDC I2C transaction. we're done here. bye bestie πŸ‘‹

🌸 SEE ALSO 🌸

  • the kernel file ./drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h β€” that's where the real lore lives, go read it iykyk πŸ“–

quick vibe check: every command up there is exactly what it says on the tin, no embellishment, no cap β€” if you need the actual register behaviour, the header is the source of truth, not me πŸ’–

that's the whole page bestie!! this one came from ./drivers/gpu/drm/mediatek and the date on it is October 2026, so yeah β€” future-coded documentation, we love to see it πŸ¦‹βœ¨ mwah, go forth and DDC πŸŽ€

πŸ“¦ where this page comes from