ENUM MEM_TYPE(9)
πΈ enum mem_type(9) πΈ
okay bestie, so this is the enum mem_type page from the Kernel API Manual β yes, the Kernel API one, that's the manual we're in π
. It's all about memory types. And if you want the full deep-dive reference (like, the actual DRAM lore), the page points you at http://en.wikipedia.org/wiki/DRAM β go wild π¦.
β¨ SYNOPSIS β¨
enum mem_type {
MEM_EMPTY ,
MEM_RESERVED ,
MEM_UNKNOWN ,
MEM_FPM ,
MEM_EDO ,
MEM_BEDO ,
MEM_SDR ,
MEM_RDR ,
MEM_DDR ,
MEM_RDDR ,
MEM_RMBS ,
MEM_DDR2 ,
MEM_FB_DDR2 ,
MEM_RDDR2 ,
MEM_XDR ,
MEM_DDR3 ,
MEM_RDDR3 ,
MEM_LRDDR3 ,
MEM_LPDDR3 ,
MEM_DDR4 ,
MEM_RDDR4 ,
MEM_LRDDR4 ,
MEM_LPDDR4 ,
MEM_DDR5 ,
MEM_RDDR5 ,
MEM_LRDDR5 ,
MEM_LPDDR5 ,
MEM_NVDIMM ,
MEM_WIO2 ,
MEM_HBM2 ,
MEM_HBM3
};
π Constants π
the whole alphabet of memory vibes, one by one, no skips π
MEM_EMPTYβ empty csrow. literally nothing in there, ghost town π»MEM_RESERVEDβ a reserved csrow type. it's reserved, bestie, back off πMEM_UNKNOWNβ unknown csrow type. we simply do not know her πMEM_FPMβ FPM β Fast Page Mode, and it was used on systems up to 1995. vintage, honestly π°οΈMEM_EDOβ EDO β Extended data out, used on systems up to 1998. also vintage, also iconic β¨MEM_BEDOβ BEDO β Burst Extended data out, which is an EDO variant. a little sequel moment πMEM_SDRβ SDR β Single data rate SDRAM, akahttp://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory. and here's the tea: they use 3 pins for chip select β pins 0 and 2 are for rank 0; pins 1 and 3 are for rank 1, if the memory is dual-rank πMEM_RDRβ Registered SDR SDRAM. registered, fancy πMEM_DDRβ Double data rate SDRAM, seehttp://en.wikipedia.org/wiki/DDR_SDRAMπ₯MEM_RDDRβ Registered Double data rate SDRAM. it's a variant of the DDR memories. a registered memory has a buffer inside it, hiding part of the memory details from the memory controller β sneaky little buffer, iykyk π«ΆMEM_RMBSβ Rambus DRAM, used on a few Pentium III/IV controllers. a few. not many. exclusive πMEM_DDR2β DDR2 RAM, as described at JEDEC JESD79-2F. those memories are labeled as"PC2-"instead of"PC"to differentiate from DDR. branding, honestly π¦MEM_FB_DDR2β Fully-Buffered DDR2, as described at JEDEC Std No. 205 and JESD206. those memories are accessed per DIMM slot, and not by a chip select signal πMEM_RDDR2β Registered DDR2 RAM. a variant of the DDR2 memories πMEM_XDRβ Rambus XDR. it's an evolution of the original RAMBUS memories, created to compete with DDR2. weren't used on any x86 arch, butcell_edacPPC memory controller uses it. niche king πMEM_DDR3β DDR3 RAM βMEM_RDDR3β Registered DDR3 RAM. a variant of the DDR3 memories πMEM_LRDDR3β Load-Reduced DDR3 memory πMEM_LPDDR3β Low-Power DDR3 memory πΈMEM_DDR4β Unbuffered DDR4 RAM π₯MEM_RDDR4β Registered DDR4 RAM. a variant of the DDR4 memories π«ΆMEM_LRDDR4β Load-Reduced DDR4 memory π¦MEM_LPDDR4β Low-Power DDR4 memory πΏMEM_DDR5β Unbuffered DDR5 RAM πMEM_RDDR5β Registered DDR5 RAM β¨MEM_LRDDR5β Load-Reduced DDR5 memory πMEM_LPDDR5β Low-Power DDR5 memory π§MEM_NVDIMMβ Non-volatile RAM. she persists πΎMEM_WIO2β Wide I/O 2 π€MEM_HBM2β High bandwidth Memory Gen 2 πMEM_HBM3β High bandwidth Memory Gen 3 ππ
π SEE ALSO π
kernel file ./include/linux/edac.h, plus the whole friend group: enum dev_type(9), enum hw_event_mc_err_type(9), enum edac_type(9), enum scrub_type(9), enum edac_mc_layer_type(9), struct edac_mc_layer(9), struct rank_info(9), struct edac_raw_error_desc(9), edac_get_dimm(9), struct edac_scrub_ops(9), struct edac_ecs_ops(9), struct edac_mem_repair_ops(9) β go read them all, no cap π
and that's the page!! this one lives under ./include/linux in the tree, and the manpage itself is dated October 2026 ποΈ β so yeah, future-coded AND iconic. mwah, see u in the next manpage bestie π«Άπ
β¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms