ENUM IPC_PHASE(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… enum ipc_phase(9) β€” Kernel API Manual ✨

okay so bestie, this is a page straight out of the Kernel API Manual, and it's all about enum ipc_phase β€” the little state machine that tracks the different AP and CP phases. πŸŽ€ It's lowkey the backbone of the whole vibe check between the application processor and the communication processor, so let's get into it.


🌸 NAME 🌸

enum ipc_phase β€” different AP and CP phases, periodt.

Here's the tea tho: the enums that are defined after "IPC_P_ROM" and before "IPC_P_RUN" indicate the operating state where the CP can respond to any requests. So like, if you're ever introducing a new phase, this shall be taken into consideration. Not optional, bestie β€” it's giving "read the room" energy. πŸ‘‘


πŸ¦‹ SYNOPSIS πŸ¦‹

enum ipc_phase {
    IPC_P_OFF ,
    IPC_P_OFF_REQ ,
    IPC_P_CRASH ,
    IPC_P_CD_READY ,
    IPC_P_ROM ,
    IPC_P_PSI ,
    IPC_P_EBL ,
    IPC_P_RUN

};

✨ Constants ✨

  • IPC_P_OFF β€” on the host PC, the PCIe device link settings are known about the combined power on, no cap. The PC is running, the driver is loaded, and the CP is in power off mode. The PCIe bus driver calls the device power mode D3hot. In this phase the driver polls the device until the device is in the power on state and signals the power mode D0. πŸŒ€
  • IPC_P_OFF_REQ β€” the intermediate phase between cleanup activity starts and ends. Like the awkward gap between leaving the group chat and actually going to sleep, yk? πŸ™ˆ
  • IPC_P_CRASH β€” the phase indicating CP crash. πŸ’€
  • IPC_P_CD_READY β€” the phase indicating CP core dump is ready. 🫢
  • IPC_P_ROM β€” after power on, CP starts in ROM mode and the IPC ROM driver is waiting 150 ms for the AP active notification saved in the PCI link status register. Literally waiting 150 whole milliseconds, iconic patience. ⏳
  • IPC_P_PSI β€” primary signed image download phase. πŸ“₯
  • IPC_P_EBL β€” extended bootloader phase. πŸ₯Ύ
  • IPC_P_RUN β€” the phase after flashing to RAM is the RUNTIME phase. That's the main character era right there. πŸ”₯
real talk: phases IPC_P_PSI and IPC_P_EBL are the ones living in that "IPC_P_ROM" β†’ "IPC_P_RUN" window, so they're the "CP can respond to any requests" girlies. Keep that in mind if you're adding new phases!! πŸ’–

πŸ‘‘ SEE ALSO πŸ‘‘

Kernel file ./drivers/net/wwan/iosm/iosm_ipc_imem.h plus the whole friend group: enum ipc_ctype(9), struct ipc_pipe(9), struct ipc_mem_channel(9), struct iosm_imem(9), ipc_imem_init(9), ipc_imem_pm_s2idle_sleep(9), ipc_imem_pm_suspend(9), ipc_imem_pm_resume(9), ipc_imem_cleanup(9), ipc_imem_irq_process(9), imem_get_device_sleep_state(9), ipc_imem_td_update_timer_suspend(9), ipc_imem_channel_close(9), ipc_imem_channel_alloc(9), ipc_imem_channel_open(9), ipc_imem_td_update_timer_start(9), ipc_imem_ul_write_td(9), ipc_imem_ul_send(9), ipc_imem_channel_update(9), ipc_imem_channel_free(9), ipc_imem_hrtimer_stop(9), ipc_imem_pipe_cleanup(9), ipc_imem_pipe_close(9), ipc_imem_phase_update(9), ipc_imem_phase_get_string(9), ipc_imem_msg_send_feature_set(9), ipc_imem_ipc_init_check(9), ipc_imem_channel_init(9), ipc_imem_devlink_trigger_chip_info(9).


okay that's the whole page bestie, go forth and phase responsibly πŸ§šπŸ’œ

this little cutie lives in ./drivers/net/wwan/iosm, dated October 2026, and it's filed under enum ipc_phase(9). mwah, bye! πŸ’…πŸŒΈ

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