ENUM INTEL_DPLL_ID(9)

✨ enum intel_dpll_id(9) ✨

okay bestie, welcome to the Kernel API Manual 🫶 — this is the page for enum intel_dpll_id, and it's literally just "possible DPLL ids". that's the whole vibe. let's go 💅

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🌸 NAME 🌸

enum intel_dpll_id — possible DPLL ids ✨

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🎀 SYNOPSIS 🎀

here's the whole enum, exactly as it lives, no notes:

enum intel_dpll_id {
    DPLL_ID_PRIVATE ,
    DPLL_ID_PCH_PLL_A ,
    DPLL_ID_PCH_PLL_B ,
    DPLL_ID_WRPLL1 ,
    DPLL_ID_WRPLL2 ,
    DPLL_ID_SPLL ,
    DPLL_ID_LCPLL_810 ,
    DPLL_ID_LCPLL_1350 ,
    DPLL_ID_LCPLL_2700 ,
    DPLL_ID_SKL_DPLL0 ,
    DPLL_ID_SKL_DPLL1 ,
    DPLL_ID_SKL_DPLL2 ,
    DPLL_ID_SKL_DPLL3 ,
    DPLL_ID_ICL_DPLL0 ,
    DPLL_ID_ICL_DPLL1 ,
    DPLL_ID_EHL_DPLL4 ,
    DPLL_ID_ICL_TBTPLL ,
    DPLL_ID_ICL_MGPLL1 ,
    DPLL_ID_ICL_MGPLL2 ,
    DPLL_ID_ICL_MGPLL3 ,
    DPLL_ID_ICL_MGPLL4 ,
    DPLL_ID_TGL_MGPLL5 ,
    DPLL_ID_TGL_MGPLL6 ,
    DPLL_ID_DG1_DPLL0 ,
    DPLL_ID_DG1_DPLL1 ,
    DPLL_ID_DG1_DPLL2 ,
    DPLL_ID_DG1_DPLL3

};

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🦋 Constants 🦋

like, the actual cast of characters, one by one (no skipping, i promise 🙈):

• DPLL_ID_PRIVATE — the non-shared dpll in use
• DPLL_ID_PCH_PLL_A — DPLL A in ILK, SNB and IVB
• DPLL_ID_PCH_PLL_B — DPLL B in ILK, SNB and IVB
• DPLL_ID_WRPLL1 — HSW and BDW WRPLL1
• DPLL_ID_WRPLL2 — HSW and BDW WRPLL2
• DPLL_ID_SPLL — HSW and BDW SPLL
• DPLL_ID_LCPLL_810 — HSW and BDW 0.81 GHz LCPLL
• DPLL_ID_LCPLL_1350 — HSW and BDW 1.35 GHz LCPLL
• DPLL_ID_LCPLL_2700 — HSW and BDW 2.7 GHz LCPLL
• DPLL_ID_SKL_DPLL0 — SKL and later DPLL0
• DPLL_ID_SKL_DPLL1 — SKL and later DPLL1
• DPLL_ID_SKL_DPLL2 — SKL and later DPLL2
• DPLL_ID_SKL_DPLL3 — SKL and later DPLL3
• DPLL_ID_ICL_DPLL0 — ICL/TGL combo PHY DPLL0
• DPLL_ID_ICL_DPLL1 — ICL/TGL combo PHY DPLL1
• DPLL_ID_EHL_DPLL4 — EHL combo PHY DPLL4
• DPLL_ID_ICL_TBTPLL — ICL/TGL TBT PLL
• DPLL_ID_ICL_MGPLL1 — ICL MG PLL 1 port 1 (C), TGL TC PLL 1 port 1 (TC1)
• DPLL_ID_ICL_MGPLL2 — ICL MG PLL 1 port 2 (D) TGL TC PLL 1 port 2 (TC2)
• DPLL_ID_ICL_MGPLL3 — ICL MG PLL 1 port 3 (E) TGL TC PLL 1 port 3 (TC3)
• DPLL_ID_ICL_MGPLL4 — ICL MG PLL 1 port 4 (F) TGL TC PLL 1 port 4 (TC4)
• DPLL_ID_TGL_MGPLL5 — TGL TC PLL port 5 (TC5)
• DPLL_ID_TGL_MGPLL6 — TGL TC PLL port 6 (TC6)
• DPLL_ID_DG1_DPLL0 — DG1 combo PHY DPLL0
• DPLL_ID_DG1_DPLL1 — DG1 combo PHY DPLL1
• DPLL_ID_DG1_DPLL2 — DG1 combo PHY DPLL2
• DPLL_ID_DG1_DPLL3 — DG1 combo PHY DPLL3

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💜 Description 💜

so this is the enumeration of all the possible IDs for a DPLL 🎯. one actual rule though, and it's giving important — real shared dpll ids must be >= 0. like, genuinely. >= 0. no cap. 🔥

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🌈 SEE ALSO 🌈

go look at the kernel file ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h, plus these besties:

• struct intel_dpll_state(9)
• struct dpll_info(9)
• struct intel_dpll(9)

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and that's the page 💖 this lil number lives in ./drivers/gpu/drm/i915/display, from October 2026 — slay, go read the source, ily, bye 🧚⭐