ENUM ATH5K_INT(9)
π NAME π
ok so this is enum ath5k_int(9) β the Hardware interrupt masks helpers, bestie. it's giving "let me introduce you to the entire interrupt alphabet" and honestly? iconic.
β¨ SYNOPSIS β¨
like, here's the whole squad, in order, no cap:
enum ath5k_int {
AR5K_INT_RXOK ,
AR5K_INT_RXDESC ,
AR5K_INT_RXERR ,
AR5K_INT_RXNOFRM ,
AR5K_INT_RXEOL ,
AR5K_INT_RXORN ,
AR5K_INT_TXOK ,
AR5K_INT_TXDESC ,
AR5K_INT_TXERR ,
AR5K_INT_TXNOFRM ,
AR5K_INT_TXEOL ,
AR5K_INT_TXURN ,
AR5K_INT_MIB ,
AR5K_INT_SWI ,
AR5K_INT_RXPHY ,
AR5K_INT_RXKCM ,
AR5K_INT_SWBA ,
AR5K_INT_BRSSI ,
AR5K_INT_BMISS ,
AR5K_INT_FATAL ,
AR5K_INT_BNR ,
AR5K_INT_TIM ,
AR5K_INT_DTIM ,
AR5K_INT_DTIM_SYNC ,
AR5K_INT_GPIO ,
AR5K_INT_BCN_TIMEOUT ,
AR5K_INT_CAB_TIMEOUT ,
AR5K_INT_QCBRORN ,
AR5K_INT_QCBRURN ,
AR5K_INT_QTRIG ,
AR5K_INT_GLOBAL ,
AR5K_INT_TX_ALL ,
AR5K_INT_RX_ALL ,
AR5K_INT_COMMON ,
AR5K_INT_NOCARD
};
π Constants π
okay bestie, member-by-member, let's go π«Ά
AR5K_INT_RXOKβ frame received, successfully, slay πAR5K_INT_RXDESCβ request RX descriptor / read RX descriptor, it's giving "gimme the paperwork"AR5K_INT_RXERRβ the frame reception flopped πAR5K_INT_RXNOFRMβ no frame showed up within a specified time period, ghosted fr frAR5K_INT_RXEOLβ hit "End Of List", which literally means we need more RX descriptors. more. descriptors. now.AR5K_INT_RXORNβ we got an RX FIFO overrun. and listen: Rx overrun is not always fatal, on some chips we can keep operating without resetting the card β that's exactly whyAR5K_INT_FATALis not common for all chips. keep that in mind, it matters.AR5K_INT_TXOKβ frame transmission success, we love a win β¨AR5K_INT_TXDESCβ request TX descriptor / read TX status descriptorAR5K_INT_TXERRβ frame transmission failure, tragic, moving on πAR5K_INT_TXNOFRMβ no frame was transmitted within a specified time period, awkwardAR5K_INT_TXEOLβ received End Of List for VEOL (Virtual End Of List). the Queue Control Unit (QCU) only signals an EOL interrupt if a descriptor's LinkPtr isNULL. for more details, go read: "http://www.freepatentsonline.com/20030225739.html"AR5K_INT_TXURNβ we got a TX FIFO underrun. in that case we should increase the TX trigger threshold. that's the whole mood.AR5K_INT_MIBβ this one means either the Management Information Base counters or one of the PHY error counters hit the maximum value and should be read and clearedAR5K_INT_SWIβ software triggered interrupt. she's self-made πAR5K_INT_RXPHYβ RX PHY ErrorAR5K_INT_RXKCMβ RX Key cache missAR5K_INT_SWBAβ SoftWare Beacon Alert β it indicates it's time to send a beacon that must be handled in software. the alternative? if you have VEOL support, you let the hardware deal with things. main character hardware energy.AR5K_INT_BRSSIβ beacon received with an RSSI value below our threshold π¬AR5K_INT_BMISSβ if you're in STA mode, this means we've stopped seeing beacons from the AP we've associated with, so we should probably try to reassociate. when in IBSS mode, this might mean we haven't received any beacons from any local stations. note that every station in an IBSS schedules to send beacons at the Target Beacon Transmission Time (TBTT) with a random backoff. okay that's a lot but it's important π«ΆAR5K_INT_FATALβ fatal errors were encountered, typically caused by bus/DMA errors, and it indicates we need to reset the card. yes, full reset. not a vibe.AR5K_INT_BNRβ beacon queue got triggered (DMA beacon alert) while emptyAR5K_INT_TIMβ beacon with local station's TIM bit setAR5K_INT_DTIMβ beacon with DTIM bit and zero DTIM count receivedAR5K_INT_DTIM_SYNCβ DTIM sync lost πAR5K_INT_GPIOβ GPIO interrupt is used for RF Kill switches connected to our GPIO pinsAR5K_INT_BCN_TIMEOUTβ beacon timeout, we waited after TBTT but got noting (that's the original's typo, keeping it π)AR5K_INT_CAB_TIMEOUTβ we waited for CAB traffic after the beacon but got nothing, or an incomplete CAB frame sequence. ghosted, again.AR5K_INT_QCBRORNβ a queue got it's CBR counter expiredAR5K_INT_QCBRURNβ a queue got triggered wile emptyAR5K_INT_QTRIGβ a queue got triggeredAR5K_INT_GLOBALβ used to clear and set the IERAR5K_INT_TX_ALLβ mask to identify all TX related interruptsAR5K_INT_RX_ALLβ mask to identify all RX related interruptsAR5K_INT_COMMONβ common interrupts shared among MACs with the same bit valueAR5K_INT_NOCARDβ signals the card has been removed π yes, gone. bye.
πΈ Description πΈ
so, the lore: these are mapped to take advantage of some common bits between the MACs, so we can set intr properties easier. some of them are not used yet inside hw.c. most map to the respective hw interrupt value as they are common among different MACs. that's the tea π
π¦ SEE ALSO π¦
kernel file ./drivers/net/wireless/ath/ath5k/ath5k.h enum
ath5k_version(9), enum ath5k_radio(9), Atheros XR(9), Atheros SuperAG(9), enum ath5k_driver_mode(9), enum ath5k_ant_mode(9), enum ath5k_bw_mode(9), struct ath5k_tx_status(9), enum ath5k_tx_queue(9), enum ath5k_tx_queue_subtype(9), enum ath5k_tx_queue_id(9), struct ath5k_txq(9), struct ath5k_txq_info(9), enum ath5k_pkt_type(9), struct ath5k_rx_status(9), enum ath5k_rfgain(9), struct ath5k_gain(9), struct ath5k_athchan_2ghz(9), enum ath5k_dmasize(9), Rate codes(9), enum ath5k_calibration_mask(9), enum ath5k_power_mode(9)
that's the whole page bestie, go read the source, it's all in ./drivers/net/wireless/ath/ath5k π«Ά
anyway that's it, ily, page from October 2026, straight out of ./drivers/net/wireless/ath/ath5k β enum ath5k_int(9), periodt π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms