DSI BRIDGE OPERATIONS(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… dsi bridge operations(9) πŸ’…

okay so bestie, this is the Kernel API Manual page for dsi bridge operations, and it is lowkey giving β€œthe rules of the DSI host bridge group chat.” 🫢 DSI host interfaces are expected to be implemented as bridges rather than encoders, but there are a few aspects of their operation that need to be defined so everyone gets a consistent interface. periodt. ✨

  • A DSI host should keep the PHY powered down until the pre_enable operation is called. All lanes are in an undefined idle state up to this point, and it must not be assumed that it is LP-11. pre_enable should initialise the PHY, set the data lanes to LP-11, and set the clock lane to either LP-11 or HS depending on the mode_flag MIPI_DSI_CLOCK_NON_CONTINUOUS. πŸ’–
  • Ordinarily the downstream bridge DSI peripheral pre_enable will have been called before the DSI host. If the DSI peripheral requires LP-11 and/or the clock lane to be in HS mode prior to pre_enable, then it can set the pre_enable_prev_first flag to request the pre_enable (and post_disable) order to be altered to enable the DSI host first. πŸ‘‘
  • Either the CRTC being enabled, or the DSI host enable operation should switch the host to actively transmitting video on the data lanes. πŸ”₯
  • The reverse also applies. The DSI host disable operation or stopping the CRTC should stop transmitting video, and the data lanes should return to the LP-11 state. The DSI host post_disable operation should disable the PHY. If the pre_enable_prev_first flag is set, then the DSI peripheral's bridge post_disable will be called before the DSI host's post_disable. 🌸
  • Whilst it is valid to call host_transfer prior to pre_enable or after post_disable, the exact state of the lanes is undefined at this point. The DSI host should initialise the interface, transmit the data, and then disable the interface again. 😭
🚨 real talk: those lane-state caveats are not a vibe to hand-wave. undefined is undefined, bestie.
  • Ultra Low Power State (ULPS) is not explicitly supported by DRM. If implemented, it therefore needs to be handled entirely within the DSI Host driver. πŸ’€

πŸ‘€ SEE ALSO πŸ‘€


πŸ¦‹ cute little sign-off: this page’s source/version vibe is ./drivers/gpu/drm, and the date stamp is October 2026. mwah, go forth and bridge responsibly πŸ’œπŸŽ€

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