CXL CORE REGION(9)

💅 cxl core region

okay so bestie, welcome to cxl core region(9) from the Kernel API Manual — section 9, no cap. CXL Regions represent mapped memory capacity in system physical address space. Whereas CXL Root Decoders identify the bounds of potential CXL Memory ranges, Regions represent the active mapped capacity by the HDM Decoder Capability structures throughout the Host Bridges, Switches, and Endpoints in the topology. 🦋✨

Region configuration has ordering constraints. UUID may be set at any time but is only visible for persistent regions. The ordering is giving very much:

1. Interleave granularity
2. Interleave size
3. Decoder targets

✨ SEE ALSO ✨

• Kernel file ./drivers/cxl/core/region.c — yes, that exact path, periodt.
• cxl_port_pick_region_decoder(9)
• cxl_port_attach_region(9)
• cxl_calc_interleave_pos(9)
• devm_cxl_add_region(9)
• cxl_validate_translation_params(9)

💖 that's the whole page, bestie — slay 💖 source/version: ./drivers/cxl/core; date: October 2026; manual page: cxl core region(9). 🎀