VC4 CRTC MODULE(9)

🎀 VC4 CRTC module(9) 🎀

okay bestie, this is the VC4 CRTC module page from the Kernel API Manual — yes, we're doing kernel display lore today and it's lowkey iconic ✨

So in VC4, the thing that matches the DRM's idea of a CRTC the closest is the Pixel Valve. The PV takes the encoder's clock plus its configuration and generates video timings from that. It also pulls scaled pixels from the HVS at that timing, and feeds it to the encoder. cute, right? 🦋

But the DRM CRTC isn't just doing timings: it also collects the configuration of all the DRM planes attached to it. Because of that, the CRTC is also responsible for writing the display list for the HVS channel that the CRTC will use. multitasking queen with main character energy 👑

The 2835 has 3 different pixel valves, and they're all a little different:

• pv0 in the audio power domain feeds DSI0 or DPI
• pv1 feeds DS1 or SMI
• pv2 in the image domain can feed either HDMI or the SDTV controller

The pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for SDTV, etc.) according to which output type is chosen in the mux. iykyk 💅

For power management, the pixel valve's registers are all clocked by the AXI clock, while the timings and FIFOs make use of the output-specific clock. And since the encoders also directly consume the CPRMAN clocks, and know what timings they need, they are the ones that set the clock. periodt 🔥

👀 SEE ALSO 👀

• Kernel file ./drivers/gpu/drm/vc4/vc4_crtc.c __vc4_crtc_init(9)

okay that's the whole vibe 🫶 stay slay, bestie — this is VC4 CRTC module(9), source/version ./drivers/gpu/drm/vc4, dated October 2026 💖✨