QUIRK FLAGS FOR DIFFERENT SAMSUNG WATCHDOG IP-CORES(9)

✨ Quirk flags for different Samsung watchdog IP-cores ✨

okay so you're in the Kernel API Manual section, and this page is literally the cheat sheet for all the quirk flags on Samsung watchdog IP-cores(9) 🐶💅 pull up a chair bestie

🌸 DESCRIPTION 🌸

So this driver is a whole multitasker — it supports multiple Samsung SoCs, and every single one of them might have a different set of registers and features supported 😭 like no two are the same, main character behavior honestly.

And here's the thing: the watchdog block sometimes requires modifying PMU registers for proper functioning, so you gotta account for register differences in both the watchdog and the PMU IP-cores. fr fr, both of them. 🙈

The quirk flags below? They exist purely to tell the driver about those SoC traits we just mentioned, and you can specify them in driver data for each particular supported device. it's giving "personalized notes for every device" and I'm obsessed 💖

🎀 THE QUIRKS 🎀

• QUIRK_HAS_WTCLRINT_REG — so the watchdog block has a WTCLRINT register. what's it for? it clears the interrupt once the interrupt service routine is complete, periodt. but listen — it's write-only 👀 writing any values to this register clears the interrupt, but reading is not permitted. nope. don't even try it.
• QUIRK_HAS_PMU_MASK_RESET — the PMU block has the register for disabling/enabling the WDT reset request. on old SoCs it's usually called MASK_WDT_RESET_REQUEST, and new SoCs have CLUSTERx_NONCPU_INT_EN instead — and heads up, that one's mask_bit value is inverted compared to the former one 🙃 yeah. inverted. keep that in mind.
• QUIRK_HAS_PMU_RST_STAT — the PMU block has the RST_STAT (reset status) register, which contains bits indicating the reason for the most recent CPU reset. if it's present, the driver will use this register to check if the previous reboot was due to a watchdog timer reset. detective mode activated 🔍
• QUIRK_HAS_PMU_AUTO_DISABLE — the PMU block has the AUTOMATIC_WDT_RESET_DISABLE register. and if the mask_bit bit is set, the PMU will disable WDT reset when the corresponding processor is in reset state. slay.
• QUIRK_HAS_PMU_CNT_EN — the PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) with a "watchdog counter enable" bit. that bit should be set to make the watchdog counter running 🏃‍♀️ like literally, that's the whole assignment.
• QUIRK_HAS_DBGACK_BIT — the WTCON register has a DBGACK_MASK bit. setting the DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. and how do we know it's in debug mode? that's determined by the DBGACK CPU signal 💀 cute.
• QUIRK_HAS_32BIT_CNT — WTDAT and WTCNT are 32-bit registers. with these 32-bit registers, larger values will be set, which means that larger timeouts value can be set 🔥 bigger numbers, longer waits, we love to see it.

🦋 SEE ALSO 🦋

• Kernel file ./drivers/watchdog/s3c2410_wdt.c struct s3c2410_wdt_variant(9)

iykyk, go read those next 💜

okay that's the whole page bestie, mwah 💋 this one came from <pink>./drivers/watchdog</pink> and it's dated October 2026 — same title energy, Quirk flags...dog IP-cores(9), and that's a wrap 🎀✨🫶