MULTI-LEVEL LMTT STRUCTURE(9)

✨ Multi-Level LMTT Structure 💅

okay bestie, welcome to the Kernel API Manual, section (9) — this is the Multi-Level LMTT Structure page, and it's honestly giving architecture-diagram main character energy. no cap, it's a picture-heavy one, so grab a lil snack 🍓 and let's vibe through it together.

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🌸 NAME 🌸

Multi-Level LMTT Structure — the multi-level LMTT setup, described for you in the Kernel API Manual, section 9. periodt. 💅

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🎀 DESCRIPTION 🎀

okay so first, two lil constants you need to hold in your head, they're literally the whole vibe check for this page:

• LMHAW (Local Memory Host Address Width) is 48 bit (256TB) 👑
• LMGAW (Local Memory Guest Address Width) is 48 bit (256TB) 👑

like, yes, both. 48 bits. 256TB. slay. ✨

and now the moment you've all been waiting for — the following figure illustrates the structure and function of the ML LMTT. it's a whole journey, ngl, but it ate:

                 LMTT L3 Directory
                 (1 Entry per VF)                                       LMTT L1 Leaf
                  +-----------+                                         +-----------+
                  |           |             LMTT L2 (per VF)            |           |
                  |           |              +-----------+              |           |
                  |           |              |           |     index:   +===========+
                  |           |              |           |     GDPA --> |    PTE    | => LMEM PF offset
                  |           |              |           |     34:21    +===========+
                  |           |    index:    |           |              |           |
                  |           |    LMEM VF   +===========+              |           |
                  |           |    offset -> |    PTE    |  ----------> +-----------+
                  |           |    GAW-1:35  +===========+              /           .
         index:   +===========+              |           |             /              .
         VFID --> |    PDE    |  --------->  +-----------+            /                 .
                  +===========+             /           /            /                    .
                  |           |           /            /            /                       .
                  +-----------+  <== [LMTT Directory Ptr]          /                          .
                 /                   /              /            /                             .
                /                  /               /       +-----------+-----------------+------+---+
               /                  /               /        | 31:HAW-16 |        HAW-17:5 |  4:1 | 0 |
              /                 /                /         +===========+=================+======+===+
             /                /                 /          |  Reserved | LMEM Page (2MB) | Rsvd | V |
            /                                   /           +-----------+-----------------+------+---+
           /                                   /
        +-----------+-----------------+------+---+
        | 63:HAW-12 |        HAW-13:4 |  3:1 | 0 |
        +===========+=================+======+===+
        |  Reserved | LMTT Ptr (64KB) | Rsvd | V |
        +-----------+-----------------+------+---+

so what's the tea in there? let me walk you through the lil legends so nothing gets lost 👇

• the LMTT L3 Directory has 1 Entry per VF, and its index is the VFID, pointing at a PDE 🦋
• from there you get the LMTT L2 (per VF) — its index is the LMEM VF offset, GAW-1:35, landing on a PTE 🌈
• and that leads to the LMTT L1 Leaf, whose index is the GDPA, bits 34:21, and that PTE gives you the LMEM PF offset ⭐
• there's also a [LMTT Directory Ptr] floating around in there pointing at the LMTT Directory, iykyk 🙈

and the two PTE bitfield layouts at the bottom, because of course there's bitfield lore:

• LMEM PTE: 31:HAW-16 = Reserved, HAW-17:5 = LMEM Page (2MB), 4:1 = Rsvd, 0 = V 💜
• LMTT directory pointer PTE: 63:HAW-12 = Reserved, HAW-13:4 = LMTT Ptr (64KB), 3:1 = Rsvd, 0 = V 💜

copy the figure exactly as it is, bestie — do not try to "fix" the bits or the spacing, the diagram is iconic and it stays fr fr 😭

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🫶 SEE ALSO 🫶

• Kernel file ./drivers/gpu/drm/xe/xe_lmtt_ml.c — go read it, go off, it's right there 📂✨

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and that's the whole page, bestie 🎀 source lives under ./drivers/gpu/drm/xe, dated October 2026, and the manual is the Multi-Level LMTT Structure(9) — mwah, study it, stan it, see you in the next one 💖🦋