MEMORY BASED INTERRUPTS(9)

💖 Memory Based Interrupts 💖

okay so bestie, welcome to the Kernel API Manual, section 9 — this one's about memory based interrupts and it's honestly such a glow-up, let me explain 🫶

✨ the whole vibe ✨

So the MMIO register based interrupts infrastructure — the one used for non-virtualized mode or SRIOV-8 (which supports 8 Virtual Functions) — does not scale efficiently to allow delivering interrupts to a large number of Virtual machines or containers. Like, it just doesn't. It's giving crowded elevator 😭

Memory based interrupt status reporting, on the other hand? It provides an efficient and scalable infrastructure. Iconic. No cap. 👑

For memory based interrupt status reporting the hardware sequence is:

• Engine writes the interrupt event to memory (Pointer to memory location is provided by SW. This memory surface must be mapped to system memory and must be marked as un-cacheable (UC) on Graphics IP Caches) 🧚
• Engine triggers an interrupt to host.

Periodt. That's the flow. 💅

🌸 SEE ALSO 🌸

• Kernel file ./drivers/gpu/drm/xe/xe_memirq.c
• Memory Based Interrupts Page Layout(9)
• xe_memirq_init(9)
• xe_memirq_source_ptr(9)
• xe_memirq_status_ptr(9)
• xe_memirq_enable_ptr(9)
• xe_memirq_init_guc(9)
• xe_memirq_reset(9)
• xe_memirq_postinstall(9)
• xe_memirq_hwe_handler(9)
• xe_memirq_guc_sw_int_0_irq_pending(9)
• xe_memirq_handler(9)

go read them, iykyk 📚✨

and that's the tea, bestie — this page lives over in ./drivers/gpu/drm/xe, dated October 2026. take care of her, she's a real one 🎀💜

bye pookie, go slay some interrupts 🦋