MEMORY BASED INTERRUPTS PAGE LAYOUT(9)

💖 Memory Based Interrupts Page Layout 💖

okay bestie, this one is straight from the Kernel API Manual, section 9, and the page is literally called Memory Based Interrupts Page Layout. It says Memory Based Interrupts requires three different objects — and yes, the specs call them "page" even though they are not page-sized or aligned. 💀

To simplify the code we allocate a single page size object and then use offsets to embedded "pages". The address of those "pages" are then programmed in the HW via LRI and LRM in the context image.

• Interrupt Status Report Page — this page contains the interrupt status vectors for each unit. Each bit in the interrupt vectors is converted to a byte, with the byte being set to 0xFF when an interrupt is triggered; interrupt vectors are 16b big so each unit gets 16B. One space is reserved for each bit in one of the GT_INTR_DWx registers, so this object needs a total of 1024B. This object needs to be 4KiB aligned. ✨
• Interrupt Source Report Page — this is the equivalent of the GT_INTR_DWx registers, with each bit in those registers being mapped to a byte here. The offsets are the same, just bytes instead of bits. This object needs to be cacheline aligned. 💅
• Interrupt Mask — the HW needs a location to fetch the interrupt mask vector to be used by the LRM in the context, so we just use the next available space in the interrupt page. 🎀

Here’s the layout, look at her:

         0x0000   +===========+  <== Interrupt Status Report Page
                  |           |
                  |           |     ____ +----+----------------+
                  |           |    /     |  0 | USER INTERRUPT |
                  +-----------+ __/      |  1 |                |
                  |  HWE(n)   | __       |    | CTX SWITCH     |
                  +-----------+         |    | WAIT SEMAPHORE |
                  |           |    ____ | 15 |                |
                  |           |          +----+----------------+
                  |           |
         0x0400   +===========+  <== Interrupt Source Report Page
                  |  HWE(0)   |
                  |  HWE(1)   |
                  |           |
                  |  HWE(x)   |
         0x0440   +===========+  <== Interrupt Enable Mask
                  |           |
                  |           |
                  +-----------+

🌈 MSI-X use case 🌈

When using MSI-X, hw engines report interrupt status and source to engine instance 0. For this scenario, in order to differentiate between the engines, we need to pass different status/source pointers in the LRC.

The requirements on those pointers are:

• Interrupt status should be 4KiB aligned
• Interrupt source should be 64 bytes aligned

To accommodate this, we duplicate the memirq page layout above — allocating a page for each engine instance and pass this page in the LRC.

Note that the same page can be reused for different engine types. For example, an LRC executing on CCS #x will have pointers to page #x, and an LRC executing on BCS #x will have the same pointers.

         0x0000   +==============================+  <== page for instance 0 (BCS0, CCS0, etc.)
                  | Interrupt Status Report Page |
         0x0400   +==============================+
                  | Interrupt Source Report Page |
         0x0440   +==============================+
                  | Interrupt Enable Mask        |
                  +==============================+
                  | Not used                     |
         0x1000   +==============================+  <== page for instance 1 (BCS1, CCS1, etc.)
                  | Interrupt Status Report Page |
         0x1400   +==============================+
                  | Interrupt Source Report Page |
         0x1440   +==============================+
                  | Not used                     |
         0x2000   +==============================+  <== page for instance 2 (BCS2, CCS2, etc.)
                  | ...                          |
                  +==============================+

👀 SEE ALSO 👀

• Kernel file ./drivers/gpu/drm/xe/xe_memirq.c — plus Memory Based Interrupts(9), xe_memirq_init(9), xe_memirq_source_ptr(9), xe_memirq_status_ptr(9), xe_memirq_enable_ptr(9), xe_memirq_init_guc(9), xe_memirq_reset(9), xe_memirq_postinstall(9), xe_memirq_hwe_handler(9), xe_memirq_guc_sw_int_0_irq_pending(9), xe_memirq_handler(9)

💖 that’s the whole page, bestie — source/version ./drivers/gpu/drm/xe, dated October 2026, from the Memory Base... Page Layout(9) footer. slay 💅