DISPLAY PLLS(9)
π Display PLLs(9) β a.k.a. the Display PLLs page from the Kernel API Manual β¨
okay so bestie, grab a π and settle in, because this one is all about Display PLLs β the literal main character clocks that drive your outputs π
πΈ DESCRIPTION πΈ
so here's the tea: the Display PLLs used for driving outputs vary by platform π¦ like, every platform does its own thing, no cap.
some platforms have per-pipe or per-encoder dedicated PLLs π β very "this is my PLL, mine only" energy. others? they let you use any PLL from a pool π which is honestly iconic and flexible of them.
and in that pool scenario π«Ά it's totally possible that multiple pipes share a PLL β but only if their configurations match. iykyk, matching configs = sharing privileges unlocked π₯
this file provides an abstraction over display PLLs β¨. the function intel_dpll_init initializes the PLLs for the given platform π§
the users of a PLL are tracked π and that tracking is integrated with the atomic modset interface. and during an atomic operation, the required PLLs can be reserved for a given CRTC and encoder configuration by calling intel_dpll_reserve π and previously reserved PLLs can be released with intel_dpll_release π β so polite, so clean.
changes to the users are first staged in the atomic state π and then made effective by calling intel_dpll_swap_state during the atomic commit phase β like the glow-up happens at commit time, periodt π
β¨ SEE ALSO β¨
the kernel file lives right here, bestie:
./drivers/gpu/drm/i915/display/intel_dpll_mgr.cπ
and the whole friend group of related pages, all of them, no skips π
intel_get_dpll_by_id(9)intel_dpll_enable(9)intel_dpll_disable(9)intel_dpll_crtc_get(9)intel_dpll_crtc_put(9)intel_dpll_swap_state(9)icl_set_active_port_dpll(9)intel_dpll_init(9)intel_dpll_compute(9)intel_dpll_reserve(9)intel_dpll_release(9)intel_dpll_update_active(9)intel_dpll_get_freq(9)intel_dpll_get_hw_state(9)intel_dpll_dump_hw_state(9)intel_dpll_compare_hw_state(9)
and that's the whole page, bestie π«Ά this beauty comes from ./drivers/gpu/drm/i915/display and it's dated October 2026 β so go forth and reserve those PLLs responsibly ππ
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms