DISPLAY PLLS(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… Display PLLs(9) β€” a.k.a. the Display PLLs page from the Kernel API Manual ✨

okay so bestie, grab a πŸ“ and settle in, because this one is all about Display PLLs β€” the literal main character clocks that drive your outputs πŸŽ€


🌸 DESCRIPTION 🌸

so here's the tea: the Display PLLs used for driving outputs vary by platform πŸ¦‹ like, every platform does its own thing, no cap.

some platforms have per-pipe or per-encoder dedicated PLLs πŸ‘‘ β€” very "this is my PLL, mine only" energy. others? they let you use any PLL from a pool πŸ’… which is honestly iconic and flexible of them.

and in that pool scenario 🫢 it's totally possible that multiple pipes share a PLL β€” but only if their configurations match. iykyk, matching configs = sharing privileges unlocked πŸ”₯

this file provides an abstraction over display PLLs ✨. the function intel_dpll_init initializes the PLLs for the given platform 🧚

the users of a PLL are tracked πŸ“‹ and that tracking is integrated with the atomic modset interface. and during an atomic operation, the required PLLs can be reserved for a given CRTC and encoder configuration by calling intel_dpll_reserve πŸ”’ and previously reserved PLLs can be released with intel_dpll_release πŸ”“ β€” so polite, so clean.

changes to the users are first staged in the atomic state πŸ™ˆ and then made effective by calling intel_dpll_swap_state during the atomic commit phase ⭐ like the glow-up happens at commit time, periodt πŸ’œ


✨ SEE ALSO ✨

the kernel file lives right here, bestie:

  • ./drivers/gpu/drm/i915/display/intel_dpll_mgr.c πŸŽ€

and the whole friend group of related pages, all of them, no skips πŸ‘‡


and that's the whole page, bestie 🫢 this beauty comes from ./drivers/gpu/drm/i915/display and it's dated October 2026 ⭐ so go forth and reserve those PLLs responsibly πŸ’–πŸ’…

πŸ“¦ where this page comes from