CDCLK RAWCLK(9)

📦 version 7.3.1, in nixpkgs unstable

💖 CDCLK / RAWCLK — the kernel API manual, section 9, bestie edition 💖

okay so sit down, grab a strawberry, because we're talking about CDCLK / RAWCLK — yes this is a section 9 kernel API man page and yes it's lowkey iconic. this is the Kernel API Manual lore and honestly it ate. 🍓✨

🌈 DESCRIPTION (the vibes, explained)

the display engine uses several different clocks to do its work, because of course it does, main character energy. but there are two main clocks involved that aren't directly related to the actual pixel clock or any symbol/bit clock of the actual output port. those two besties are:

  • the core display clock (CDCLK)
  • RAWCLK

👑 CDCLK — the queen bee

CDCLK clocks most of the display pipe logic, so its frequency must be high enough to support the rate at which pixels are flowing through the pipes. and downscaling has to be accounted for too, because that increases the effective pixel rate. math is math, periodt. ✨

on several platforms the CDCLK frequency can be changed dynamically to minimize power consumption for a given display configuration. but heads up: typically, changes to the CDCLK frequency require all the display pipes to be shut down while the frequency is being changed. no multitasking, bestie. 💅

on SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. the DMC will not change the active CDCLK frequency though, so that part is still performed by the driver directly. teamwork, i guess. 🫶

🧚 the CDCLK glow-up crew (multiple components involved in generating the CDCLK frequency)

  • the CDCLK PLL — generates an output clock based on a reference clock and a ratio parameter 🔥
  • the CD2X Divider — divides the output of the PLL based on a divisor selected from a set of pre-defined choices
  • the CD2X Squasher — further divides the output based on a waveform represented as a sequence of bits where each zero "squashes out" a clock cycle 💀
  • and finally, a fixed divider that divides the output frequency by 2

so as such, the resulting CDCLK frequency can be calculated with this formula, and no i will not gatekeep it:

cdclk = vco / cd2x_div / (sq_len / sq_div) / 2

where:

  • vco is the frequency generated by the PLL
  • cd2x_div represents the CD2X Divider
  • sq_len and sq_div are the bit length and the number of high bits for the CD2X Squasher waveform, respectively
  • 2 represents the fixed divider
ngl, some older platforms do not contain the CD2X Divider and/or CD2X Squasher — in which case we can just ignore their respective factors in the formula above. slay, less math for us. 🙈

💅 how to actually change the CDCLK frequency

several methods exist, and which ones are supported depends on the platform:

  • Full PLL disable + re-enable with new VCO frequency. pipes must be inactive. 😭
  • CD2X divider update. single pipe can be active, since the divider update can be synchronized with the pipe's start of vblank.
  • Crawl the PLL smoothly to the new VCO frequency. pipes can be active. ✨
  • Squash waveform update. pipes can be active.
  • Crawl and squash can also be done back to back. pipes can be active. 🔥

🦋 RAWCLK — the low-maintenance icon

RAWCLK is a fixed frequency clock, often used by various auxiliary blocks such as AUX CH or backlight PWM. so the only thing we really need to know about RAWCLK is its frequency, so that various dividers can be programmed correctly. that's it. that's the whole personality. 💜

🌸 SEE ALSO

kernel file ./drivers/gpu/drm/i915/display/intel_cdclk.c

and the whole friend group:

and that's the page, bestie 🎀 this little gem lives in ./drivers/gpu/drm/i915/display, it's dated October 2026, and it's filed under CDCLK / RAWCLK(9) — go forth and clock responsibly, iykyk. 💖✨👑

📦 where this page comes from