AMDGPU RAS DEBUGFS CONTROL INTERFACE(9)

💖 AMDGPU RAS debugfs control interface 💖

okay bestie, this is the Kernel API Manual page for the AMDGPU RAS debugfs control interface — and yes, it’s giving kernel-internals main character energy. ✨

The control interface accepts struct ras_debug_if, and that struct has two members. First member: ras_debug_if::head or ras_debug_if::inject.

head is used to indicate which IP block will be under control. It has four members, they are block, type, sub_block_index, name.

• block — which IP will be under control.
• type — what kind of error will be enabled/disabled/injected.
• sub_block_index — some IPs have subcomponets. say, GFX, sDMA.
• name — the name of IP.

inject has three more members than head, they are address, value and mask. As their names indicate, inject operation will write the value to the address.

The second member: struct ras_debug_if::op. It has three kinds of operations.

• 0 — disable RAS on the block. Take ::head as its data.
• 1 — enable RAS on the block. Take ::head as its data.
• 2 — inject errors on the block. Take ::inject as its data.

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🎀 How to use the interface? 🎀

In a program: copy the struct ras_debug_if in your code and initialize it. Write the struct to the control interface.

From shell:

echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl

Where N, is the card which you want to affect.

"disable" requires only the block. "enable" requires the block and error type. "inject" requires the block, error type, address, and value.

The block is one of: umc, sdma, gfx, etc. see ras_block_string[] for details.

The error type is one of: ue, ce and poison where, ue is multi-uncorrectable, ce is single-correctable, and poison is poison.

The sub-block is the sub-block index — pass 0 if there is no sub-block. The address and value are hexadecimal numbers, leading 0x is optional. The mask means instance mask, is optional, default value is 0x1.

For instance,

echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl

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🔍 How to check the result of the operation? 🔍

To check disable/enable, see "ras" features at, /sys/class/drm/card[0/1/2...]/device/ras/features

To check inject, see the corresponding error count at, /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count

⚠️ NOTE: Operations are only allowed on blocks which are supported. Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask to see which blocks support RAS on a particular asic.

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👀 SEE ALSO 👀

• Kernel file ./drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
• AMDGPU RAS debugfs EEPROM table reset interface(9)
• AMDGPU RAS sysfs Error Count Interface(9)
• amdgpu_ras_query_error_count_helper(9)
• amdgpu_ras_query_error_count(9)
• AMDGPU RAS sysfs gpu_vram_bad_pages Interface(9)
• AMDGPU RAS Reboot Behavior for Unrecoverable Errors(9)

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💖 that’s the whole page, bestie 💖 source/version footer: ./drivers/gpu/drm/amd/amdgpu; date: October 2026; footer title: AMDGPU RAS d...ol interface(9). mwah 💋✨