A DIGITAL FREQUENCY SYNTHESIZER(9)

💖 A digital frequency synthesizer 💖

okay so welcome to A digital f... synthesizer(9), bestie — it lives in the Kernel API Manual and it's lowkey iconic. The page title is literally A digital frequency synthesizer, and the header/footer are out here doing the whole ellipsis thing (A digital f... synthesizer(9)) like they forgot the rest of the word. We move. 💅

🦋 Traits of this clock

okay so here's the vibe check for this clock, no cap:

• prepare — clk_(un)prepare only ensures parent is (un)prepared. That's it. It's giving minimal effort but in a slay way. ✨
• enable — clk_enable and clk_disable are functional. They work. Periodt. 💚
• rate — set rate is functional. Functional functional. 😌
• parent — fixed parent. No clk_set_parent support — so don't come for that, bestie, because it's not there. 🙈

✨ SEE ALSO ✨

• Kernel file ./drivers/clk/st/clkgen-fsyn.c — the actual source file, iconic. 🧚
• A Frequency Synthesizer that multiples its input clock by a fixed factor(9) — yes, "multiples" is exactly how it's written, I'm not fixing the typo, I'm just reporting it. iykyk. 🍓
• struct st_clk_quadfs_pll(9) — struct bestie, go read it. obsessed. 💜

made with 💅 from the source/version ./drivers/clk/st, dated October 2026, and forever filed under A digital f... synthesizer(9). iykyk 🫶✨