A FREQUENCY SYNTHESIZER THAT MULTIPLES ITS INPUT CLOCK BY A FIXED FACTOR(9)

💅 A Frequency ...fixed factor(9) 💅

okay so we're in the Kernel API Manual, bestie — yes, literally the Kernel API Manual — and this page is about a frequency synthesizer that multiples its input clock by a fixed factor. No cap, that's the whole vibe. 🦋

🌸 NAME 🌸

A Frequency Synthesizer that multiples its input clock by a fixed factor

🦋 DESCRIPTION 🦋

Traits of this clock — and yes, every single one made the list, because we don't skip details in this group chat:

• prepare — clk_(un)prepare only ensures parent is (un)prepared
• enable — clk_enable and clk_disable are functional & control the Fsyn
• rate — inherits rate from parent.
• set_rate/round_rate/recalc_rate
• parent — fixed parent. No clk_set_parent support

🔥 SEE ALSO 🔥

• Kernel file ./drivers/clk/st/clkgen-fsyn.c struct st_clk_quadfs_pll(9), A digital frequency synthesizer(9)

xoxo, your kernel bestie 💅 — source/version: ./drivers/clk/st; date: October 2026; page title: A Frequency ...fixed factor(9)