ctags-lang-verilog(7)

📦
version 6.2.1 · 3 versions
, in ubuntu resolute, ubuntu stonking

ctags-lang-verilog 💖

okay bestie, gather round, because this is the manual page for the SystemVerilog/Verilog parser in Universal Ctags — yes it's ctags-lang-verilog(7), no it's not boring, sit with me. 🧚

✨ SYNOPSIS ✨

ctags ... [--kinds-systemverilog=+Q] [--fields-SystemVerilog=+{parameter}] ...
ctags ... [--fields-Verilog=+{parameter}] ...

and here's the little language cheat sheet, because mapping vibes matter:

  • Language SystemVerilog → Language ID SystemVerilog → File Mapping .sv, .svh, svi
  • Language Verilog → Language ID Verilog → File Mapping .v

🌸 DESCRIPTION 🌸

So this page is all about the SystemVerilog/Verilog parser for Universal Ctags. The SystemVerilog parser supports IEEE Std 1800-2017 keywords, and the Verilog parser supports IEEE Std 1364-2005 keywords. periodt. 💅

👑 Supported Kinds

run this and watch it slay:

$ ctags --list-kinds-full=SystemVerilog
#LETTER NAME       ENABLED REFONLY NROLES MASTER DESCRIPTION
A       assert     yes     no      0      NONE   assertions (assert, assume, cover, restrict)
C       class      yes     no      0      NONE   classes
E       enum       yes     no      0      NONE   enumerators
H       checker    yes     no      0      NONE   checkers
I       interface  yes     no      0      NONE   interfaces
K       package    yes     no      0      NONE   packages
L       clocking   yes     no      0      NONE   clocking
M       modport    yes     no      0      NONE   modports
N       nettype    yes     no      0      NONE   nettype declarations
O       constraint yes     no      0      NONE   constraints
P       program    yes     no      0      NONE   programs
Q       prototype  no      no      0      NONE   prototypes (extern, pure)
R       property   yes     no      0      NONE   properties
S       struct     yes     no      0      NONE   structs and unions
T       typedef    yes     no      0      NONE   type declarations
V       covergroup yes     no      0      NONE   covergroups
b       block      yes     no      0      NONE   blocks (begin, fork)
c       constant   yes     no      0      NONE   constants (parameter, specparam, enum values)
d       define     yes     no      0      NONE   text macros
e       event      yes     no      0      NONE   events
f       function   yes     no      0      NONE   functions
i       instance   yes     no      0      NONE   instances of module or interface
l       ifclass    yes     no      0      NONE   interface class
m       module     yes     no      0      NONE   modules
n       net        yes     no      0      NONE   net data types
p       port       yes     no      0      NONE   ports
q       sequence   yes     no      0      NONE   sequences
r       register   yes     no      0      NONE   variable data types
t       task       yes     no      0      NONE   tasks
w       member     yes     no      0      NONE   struct and union members
heads up bestie: prototype (Q) is disabled by default. it's the shy one. 🙈

and the Verilog list, equally iconic:

$ ctags --list-kinds-full=Verilog
#LETTER NAME     ENABLED REFONLY NROLES MASTER DESCRIPTION
b       block    yes     no      0      NONE   blocks (begin, fork)
c       constant yes     no      0      NONE   constants (parameter, specparam)
d       define   yes     no      0      NONE   text macros
e       event    yes     no      0      NONE   events
f       function yes     no      0      NONE   functions
i       instance yes     no      0      NONE   instances of module
m       module   yes     no      0      NONE   modules
n       net      yes     no      0      NONE   net data types
p       port     yes     no      0      NONE   ports
r       register yes     no      0      NONE   variable data types
t       task     yes     no      0      NONE   tasks

🎀 Supported Language Specific Fields

the field situation, fresh off the press:

$ ctags --list-fields=Verilog
#LETTER NAME      ENABLED LANGUAGE JSTYPE FIXED DESCRIPTION
-       parameter no      Verilog  --b    no    parameter whose value can be overridden.
$ ctags --list-fields=SystemVerilog
#LETTER NAME      ENABLED LANGUAGE      JSTYPE FIXED DESCRIPTION
-       parameter no      SystemVerilog --b    no    parameter whose value can be overridden.

🦋 the parameter field

okay so if the field parameter is enabled, a field parameter: gets added onto a parameter whose value can be overridden on an instantiated module, interface, or program. it's giving very useful — for an editor plugin or extension that wants to auto-instantiate modules with parameters that can be overridden. obsessed. ✨

$ ctags ... --fields-Verilog=+{parameter} ...
$ ctags ... --fields-SystemVerilog=+{parameter} ...

on the source code below, the fields parameter: land on the parameters P*, and not on the ones L*. and ngl, watch out: L4 and L6 are declared by a parameter statement, but the fields parameter: are not added, because they cannot be overridden. no cap.

"input.sv"

// compilation unit scope
parameter L1 = "synonym for the localparam";

module with_parameter_port_list #(
        P1,
        localparam L2 = P1+1,
        parameter P2)
        ( /*port list...*/ );
        parameter  L3 = "synonym for the localparam";
        localparam L4 = "localparam";
        // ...
endmodule

module with_empty_parameter_port_list #()
        ( /*port list...*/ );
        parameter  L5 = "synonym for the localparam";
        localparam L6 = "localparam";
        // ...
endmodule

module no_parameter_port_list
        ( /*port list...*/ );
        parameter  P3 = "parameter";
        localparam L7 = "localparam";
        // ...
endmodule

and the output, look at her go 💅:

$ ctags -uo - --fields-SystemVerilog=+{parameter} input.sv
L1      input.sv        /^parameter L1 = "synonym for the localparam";$/;"      c       parameter:
with_parameter_port_list        input.sv        /^module with_parameter_port_list #($/;"        m
P1      input.sv        /^      P1,$/;" c       module:with_parameter_port_list parameter:
L2      input.sv        /^      localparam L2 = P1+1,$/;"       c       module:with_parameter_port_list
P2      input.sv        /^      parameter P2)$/;"       c       module:with_parameter_port_list parameter:
L3      input.sv        /^      parameter  L3 = "synonym for the localparam";$/;"       c       module:with_parameter_port_list
L4      input.sv        /^      localparam L4 = "localparam";$/;"       c       module:with_parameter_port_list
with_empty_parameter_port_list  input.sv        /^module with_empty_parameter_port_list #()$/;" m
L5      input.sv        /^      parameter  L5 = "synonym for the localparam";$/;"       c       module:with_empty_parameter_port_list
L6      input.sv        /^      localparam L6 = "localparam";$/;"       c       module:with_empty_parameter_port_list
no_parameter_port_list  input.sv        /^module no_parameter_port_list$/;"     m
P3      input.sv        /^      parameter  P3 = "parameter";$/;"        c       module:no_parameter_port_list   parameter:
L7      input.sv        /^      localparam L7 = "localparam";$/;"       c       module:no_parameter_port_list

🌈 Supported Roles

$ ./ctags --list-roles=SystemVerilog
#KIND(L/N) NAME ENABLED DESCRIPTION
m/module   decl on      declaring instances

$ ./ctags --list-roles=Verilog
#KIND(L/N) NAME ENABLED DESCRIPTION
m/module   decl on      declaring instances

so the parser pulls the names of modules used in instance declarations out as reference tags, and decl is the role for those tags. if you wanna know more about reference tags and roles, go read the "TAG ENTRIES" section of ctags(1). iykyk. 📖

Warning: the support for references in Universal Ctags is still experimental — the names of the roles may be changed in the future. don't get too attached bestie 😭

⭐ TIPS

if you want to map files *.v to SystemVerilog, just add the option --langmap=SystemVerilog:.v. easy slay.

💀 KNOWN ISSUES 💀

go look at <https://github.com/universal-ctags/ctags/issues/2674> for more information.

🍓 VERSIONS 🍓

Change since "0.0"

  • New kind define

🫶 SEE ALSO 🫶

k that's the whole thing, bestie!! 💖 this page is from Universal Ctags version 6.2.1, and yeah the man page family is ctags-lang-verilog(7) — go forth and parse, main character energy only. 🎀✨🦋

📦 where this page comes from