SXLIB(5)

📦 version 5.1.1, in fedora 43, fedora 44

SXLIB(5) — CAO-VLSI Reference Manual 💖

okay bestie, sit DOWN, we're doing the standard cell library tour and it's a long one so buckle up 🎀 this is sxlib(5), from the CAO-VLSI Reference Manual, and I'm gonna walk you through every single thing in here, no skips, no cap.

✨ NAME ✨

sxlib — a portable CMOS Standard Cell Library 💅

🌸 ORIGIN 🌸

so this software belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at the LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France 🇫🇷 (yes, the Paris one, main character energy fr)

🦋 DESCRIPTION 🦋

the sxlib library contains standard cells that were developed at UPMC-ASIM/LIP6, and this manual is giving you the full list of available cells — their behavior, their width, their maximum delay and their input fan-in. it also gives you a few thumb rules so you can actually use these cells well 🫶

heads up: the delays listed here are the maximum ones, meaning worst case for a generic .35 micron process. if you want more precise delay numbers, go look in the ALLIANCE VHDL behavior files (the .vbe file). 📁

also, the cell name is built like this: <behavior>_<output drive> — explanations for that are below, keep reading.

Four files are attached to each cell:

  • ALLIANCE Layout ............... cell-name.ap
  • ALLIANCE Transistor net-list .. cell-name.al
  • ALLIANCE VHDL behavior ........ cell-name.vbe
  • Compiled HILO behavior ........ 0000000xx.dat

And a few files more:

  • CATAL ......................... ALLIANCE catalog file
  • sxlib.cct ..................... Cell definition for HILO CAD tools
  • CIRCUIT.idx ................... HILO catalog file
  • sxlib.lib ..................... Cell definition for Synopsys CAD tools
  • sxlib.db ...................... Compiled cell definition for Synopsys
  • sxlib.sdb ..................... Icon definition for Synopys

💜 PHYSICAL OUTLINE 💜

sxlib uses the symbolic layout promoted by Alliance so that you get process independence, periodt. all dimensions are in lambda units ✨ and the mapping to a specific process CIF or GDS2 layout has to be done by the s2r tool (symbolic to real), which uses a value for the lambda (e.g. 1 lambda=0.3um).

              _________________
          50 |       VDD       |
          45 |_________________|     x : place of virtual connector.
          40 |           x     |
          35 |        x  x     |         they are named : name_<y>
          30 |  x     x        |
          25 |  x     x        |         for example : i0_20
          20 |  x              |                       i0_25
          15 |           x     |                       i0_30
          10 |_________________|
           5 |       VSS       |
           0 |_________________|
             0  5 10 15 20 25 30

every single cell is 50 lambdas high and N times 5 lambdas wide, where N is the number of pitches. that's literally the only physical info given in the cell list below, bestie. 😌

  • power supplies live in horizontal ALU1 and are 6 lambdas wide ⚡
  • connectors are inside the cells, placed on a 5x5 grid 🎯
  • half layout design rules are a warranty for any layer on any face — except for the power supply and NWELL ⚠️
  • cells can be abutted in all directions whenever the supply is well connected, and connectors are always placed on the 5x5 grid 👑

⏱️ DELAY MODEL ⏱️

so the cells have been extracted and simulated using a generic 0.35um process to give realistic values for delays and capacitances. we chose to give only the worst delay for each output signal — which is lowkey not very realistic, since delay depends on each input and one input can easily be up to twice as fast as another 🙈 — but honestly we just wanted to give you an idea of the relative delay.

also, we added 0.6ns to each output delay to take into account the delay due to signal commutation. we assumed the output drives the maximum capacitance. this capacitance was computed like this: we considered that a good slope signal for this process was 0.8ns, then we searched for the capacitance required to get the same input and output slope (0.8ns) for the smaller inverter (inv_x1). that was 125fF. then we simulated the same inverter without output capacitance, and the delay difference was about 0.6ns. this result isn't exactly the same for all cells, but 0.6ns is a good approximation. 💫

so the given delay is a worst case (70degree, 2.7Volt, slow process, worst input). want an idea of the typical delay? divide the worst delay by 1.5. best delay? divide by 2. more detailed data lives in the GENERIC data included in the VHDL files (.vbe), and examples are at the end of this manual. 📚

lastly — and this is the real tea — to get a very better idea about the real delay without simulating the spice transistor netlist, you need to use the TAS (1) tool, which is a timing static analyzer able to give the longer and the shorter path for a given process. slay. 💅

🔥 OUTPUT DRIVE 🔥

the output drive of a cell tells you how good the cell is at driving a big capacitance. this faculty depends on the rising and falling output resistance — the smaller the resistance, the bigger the capacitance it can handle. minimum drive is x1, which corresponds to the smallest available inverter (inv_x1). x2 means the cell is equivalent (from the driving point of view) to two smaller inverters in parallel, and so on. 🔁

the maximum output drive is x8, and it's limited because of the maximum output slope and the maximum authorized instantaneous current. if it were bigger, the output slope could be very tight and the current too big. 🛑

with the 0.35um process, an x1 can drive about 125fF, x2 -> 250fF, x4 -> 500fF, x8 -> 1000fF. this is just an indication, since if a cell is overloaded the only consequence is that the propagation time goes up. on the other hand, it's not great to under-load a cell either, because that leads to signal overshoot 😬

actually, for big gates such as noa3ao322_x1, x1 means the maximal driving strength reachable with a single logic layer, which can be much less than an inv_x1. that's why the cell list below contains more precise drive strength. as you can see, noa3ao322_x1 has an output drive strength of 0.6, meaning 0.6 times an inverter — so it can drive about 0.6*125fF=75fF. 🧮

with the 0.35um process, a 1 lambda interconnect wire is about 0.15fF, and an average cell fan-in is 10fF. so if it takes about 50 lambdas to connect 2 cells, an x1 cell is able to drive about 7 cells (125/(10+50*.15)=7). with 100 lambdas, 5 cells. with 750 lambdas, only 2 cells. and note that 50 lambdas means the cells are very close to each other, nearly abutted, while 100 lambdas is an average value. 📏

all of this is just indications. only a timing analysis on the extracted transistor net-list from layout can tell if a cell is well used or not (see tas(1) for info about static timing analysis). no shortcuts, bestie. 💯

🧠 BEHAVIOR 🧠

for most cells, you can figure out the behavior just by reading the name. super intuitive for an inverter, a bit more complex for and/or cells. for those, the name gives you the and/or tree structure. and the input order for the VHDL interface component is always the alphabetic order. 🔤

inv           : inversor buffer
buf           : buffer
[n]ts         : [not] tree-state
[n]xr<i>      : [not] xor <i> inputs
[n]mx<i>      : [not] multiplexor <i> inputs with coded command
[n][sd]ff<i>  : [not] [static|dynamic] flip-flop <i> inputs
[n]oa...      : [not] and/or function (see below)

and_or cell (YACC (1) grammar):-

NAME     : n OA_CELL                 -> not OA_CELL
         | OA_CELL                   -> OA_CELL

OA_CELL  : OPERATOR INPUTS           -> function with INPUTS inputs
         | OPERATOR OA_CELLS INPUTS  -> function with INPUTS inputs
                                        where some inputs are OA_CELL

OPERATOR : a                         -> and
         | o                         -> or
         | n                         -> not

OA_CELLS : OA_CELLS OA_CELL          -> list of OA_CELL
         | OA_CELL                   -> last OA_CELL of the list

INPUTS   : integer                   -> number of inputs

the input names are implicit and formed that way: i<number>. they're attributed in order, beginning with i0. 🔢

nx where x is a number means there are x inverters in parallel. for example, an23 is an and with 3 inputs of which two are inverted, that is and( not(i0), not(i1), i2). 🎀

examples (and yeah, some of these are not in sxlib):

na2       : not( and(i0,i1))
on12      : or( not(i0), i1)
noa2a22   : not( or( and(i0,i1), and(i2,i3)))
noa23     : not( or( and(i0,i1), i3))
noao22a34 : not( or( and( or(i0,i1), i2), and(i3,i4,i5), i6, i7))
note that xr2 could not be expressed with an and/or formula even if xr2 = or( and( not(i0), i1), and( not(i1), i0)) = oan12an122 — but the input names are not well distributed. 💀

okay we're not done yet bestie, there's more coming — don't go anywhere 💖✨

🧮 CELL LIST

Okay bestie, here's the whole menu of cells you get. Every single one. No skipping, no "eh you get the vibe" — we're doing this properly. 💅

  • First column = the pitch width. The pitch value is 5 lambdas, the height is 50, so the area works out to <number>*5*50.
  • Second column = the output drive strength, measured against the inv_x1 output drive strength (scroll back up to OUTPUT DRIVE if you need the lore 🫶).
  • Third column = the delay in nano-seconds. And remember, this delay is the one for the slower input +0.6ns (that's the DELAY MODEL tea from earlier).
  • Last column = the function behavior, with input capacitance attached. Here's the secret decoder ring: / means not, + means or, . means and, ^ means xor. Every input is followed by its fan-in capacitance in fF — so like, i0<11> means the i0 pin capacitance is 11fF. Periodt.
Real talk moment: for some cells, like fulladder, it just wasn't possible to hook up all the inputs internally. So there are several inputs you have to connect yourself from the outside. In the list below, those inputs get a little star (*) after them in the equation. ⭐

So for example, the fulladder equation is sout <= (a* . b* . cin*). That a* is standing in for a0, a1, a2, a3 — which you have to explicitly connect. Not us. You. 🙈

Also, heads up: a few cells have more than one output. When that happens, you'll see several lines in the list, one per output. Easy.

=================================================================
WIDTH NAME  DRIVE DELAY BEHAVIOR with cin
-------------------------------------------------------- INVERSOR

🚫 INVERSOR (inverters, they invert)

  • inv_x1 — width 3, drive 1.0, delay 0.7, nq <= /i<8>
  • inv_x2 — width 3, drive 1.6, delay 0.7, nq <= /i<12>
  • inv_x4 — width 4, drive 3.6, delay 0.7, nq <= /i<26>
  • inv_x8 — width 7, drive 8.4, delay 0.7, nq <= /i<54>
---------------------------------------------------------- BUFFER

🦋 BUFFER

  • buf_x2 — width 4, drive 2.1, delay 1.0, q <= i<6>
  • buf_x4 — width 5, drive 4.3, delay 1.0, q <= i<9>
  • buf_x8 — width 8, drive 8.4, delay 1.0, q <= i<15>
------------------------------------------------------ THREE STATE

🎭 THREE STATE

  • nts_x1 — width 6, drive 1.2, delay 0.8, IF (cmd<14>) nq <= /i<14>
  • nts_x2 — width 8, drive 2.4, delay 0.9, IF (cmd<18>) nq <= /i<28>
  • ts_x4 — width 10, drive 4.3, delay 1.1, IF (cmd<19>) q <= i<8>
  • ts_x8 — width 13, drive 8.4, delay 1.2, IF (cmd<19>) q <= i<8>
-------------------------------------------------------------- AND

✨ AND

  • na2_x1 — width 4, drive 1.0, delay 0.9, nq <= /(i0<11>.i1<11>)
  • na2_x4 — width 7, drive 4.3, delay 1.2, nq <= /(i0<10>.i1<10>)
  • na3_x1 — width 5, drive 0.9, delay 1.0, nq <= /(i0<11>.i1<11>.i2<11>)
  • na3_x4 — width 8, drive 4.3, delay 1.3, nq <= /(i0<10>.i1<10>.i2<10>)
  • na4_x1 — width 6, drive 0.7, delay 1.0, nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
  • na4_x4 — width 10, drive 4.3, delay 1.4, nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
  • a2_x2 — width 5, drive 2.1, delay 1.0, q <= (i0<9>.i1<11>)
  • a2_x4 — width 6, drive 4.3, delay 1.1, q <= (i0<9>.i1<11>)
  • a3_x2 — width 6, drive 2.1, delay 1.1, q <= (i0<10>.i1<10>.i2<10>)
  • a3_x4 — width 7, drive 4.3, delay 1.2, q <= (i0<10>.i1<10>.i2<10>)
  • a4_x2 — width 7, drive 2.1, delay 1.2, q <= (i0<10>.i1<10>.i2<10>.i3<10>)
  • a4_x4 — width 8, drive 4.3, delay 1.3, q <= (i0<10>.i1<10>.i2<10>.i3<10>)
  • an12_x1 — width 5, drive 1.0, delay 1.0, q <= (/i0<12>).i1<9>
  • an12_x4 — width 8, drive 4.3, delay 1.1, q <= (/i0<9>).i1<11>
--------------------------------------------------------------- OR

🌸 OR

  • no2_x1 — width 4, drive 1.0, delay 0.9, nq <= /(i0<12>+i1<12>)
  • no2_x4 — width 8, drive 4.3, delay 1.2, nq <= /(i0<12>+i1<11>)
  • no3_x1 — width 5, drive 0.8, delay 1.0, nq <= /(i0<12>+i1<12>+i2<12>)
  • no3_x4 — width 8, drive 4.3, delay 1.3, nq <= /(i0<12>+i1<12>+i2<11>)
  • no4_x1 — width 6, drive 0.6, delay 1.1, nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
  • no4_x4 — width 10, drive 4.3, delay 1.4, nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
  • o2_x2 — width 5, drive 2.1, delay 1.0, q <= (i0<10>+i1<10>)
  • o2_x4 — width 6, drive 4.3, delay 1.1, q <= (i0<10>+i1<10>)
  • o3_x2 — width 6, drive 2.1, delay 1.1, q <= (i0<10>+i1<10>+i2<9>)
  • o3_x4 — width 10, drive 4.3, delay 1.2, q <= (i0<10>+i1<10>+i2<9>)
  • o4_x2 — width 7, drive 2.1, delay 1.2, q <= (i0<10>+i1<10>+i2<10>+i3<9>)
  • o4_x4 — width 8, drive 4.3, delay 1.3, q <= (i0<12>+i1<12>+i2<12>+i3<12>)
  • on12_x1 — width 5, drive 1.0, delay 0.9, q <= (/i0<11>)+i1<9>
  • on12_x4 — width 8, drive 4.3, delay 1.1, q <= (/i0<9>)+i1<10>
--------------------------------------------------------- AND/OR 3

🧚 AND/OR 3

  • nao22_x1 — width 6, drive 1.2, delay 0.9, nq <= /((i0<14>+i1<14>).i2<14>)
  • nao22_x4 — width 10, drive 4.3, delay 1.3, nq <= /((i0<8> +i1<8>) .i2<9>)
  • noa22_x1 — width 6, drive 1.2, delay 0.9, nq <= /((i0<14>.i1<14>)+i2<14>)
  • noa22_x4 — width 10, drive 4.3, delay 1.3, nq <= /((i0<8> .i1<8>) +i2<9>)
  • ao22_x2 — width 6, drive 2.1, delay 1.2, q <= ((i0<8>+i1<8>).i2<9>)
  • ao22_x4 — width 8, drive 4.3, delay 1.3, q <= ((i0<8>+i1<8>).i2<9>)
  • oa22_x2 — width 6, drive 2.1, delay 1.2, q <= ((i0<8>.i1<8>)+i2<9>)
  • oa22_x4 — width 8, drive 4.3, delay 1.3, q <= ((i0<8>.i1<8>)+i2<9>)
--------------------------------------------------------- AND/OR 4

💖 AND/OR 4

  • nao2o22_x1 — width 7, drive 1.2, delay 1.0, nq <= /((i0<14>+i1<14>).(i2<14>+i3<14>))
  • nao2o22_x4 — width 11, drive 4.3, delay 1.4, nq <= /((i0<8> +i1<8>) .(i2<8> +i3<8>))
  • noa2a22_x1 — width 7, drive 1.2, delay 1.0, nq <= /((i0<14>.i1<14>)+(i2<14>.i3<14>))
  • noa2a22_x4 — width 11, drive 4.3, delay 1.4, nq <= /((i0<8> .i1<8>) +(i2<8> .i3<8>))
  • ao2o22_x2 — width 9, drive 2.1, delay 1.2, q <= ((i0<8>+i1<8>).(i2<8>+i3<8>))
  • ao2o22_x4 — width 10, drive 4.3, delay 1.3, q <= ((i0<8>+i1<8>).(i2<8>+i3<8>))
  • oa2a22_x2 — width 9, drive 2.1, delay 1.2, q <= ((i0<8>.i1<8>)+(i2<8>.i3<8>))
  • oa2a22_x4 — width 10, drive 4.3, delay 1.4, q <= ((i0<8>.i1<8>)+(i2<8>.i3<8>))
--------------------------------------------------------- AND/OR 5

⭐ AND/OR 5

  • noa2ao222_x1 — width 7, drive 0.7, delay 1.1, nq <= /((i0<11>.i1<11>)+((i2<13>+i3<13>).i4<13>))
  • noa2ao222_x4 — width 11, drive 4.3, delay 1.4, nq <= /((i0<11>.i1<11>)+((i2<11>+i3<11>).i4<11>))
  • oa2ao222_x2 — width 10, drive 2.1, delay 1.2, q <= ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
  • oa2ao222_x4 — width 11, drive 4.3, delay 1.3, q <= ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
--------------------------------------------------------- AND/OR 6

🎀 AND/OR 6

  • noa2a2a23_x1 — width 10, drive 0.8, delay 1.2, nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>) +(i4<14>.i5<14>))
  • noa2a2a23_x4 — width 13, drive 4.3, delay 1.3, nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>) +(i4<14>.i5<14>))
  • oa2a2a23_x2 — width 12, drive 2.1, delay 1.4, q <= ((i0<13>.i1<14>) +(i2<14>.i3<14>) +(i4<14>.i5<14>))
  • oa2a2a23_x4 — width 13, drive 4.3, delay 1.4, q <= ((i0<13>.i1<14>) +(i2<14>.i3<14>) +(i4<14>.i5<14>))
--------------------------------------------------------- AND/OR 7

🍓 AND/OR 7

  • noa3ao322_x1 — width 9, drive 0.6, delay 1.2, nq <= /((i0<13>.i1<13>.i2<12>) +((i3<13>+i4<13>+i5<13>).i6<13>))
  • noa3ao322_x4 — width 11, drive 4.3, delay 1.4, nq <= /((i0<10>.i1<9>.i2<9>) +((i3<9>+i4<9>+i5<9>).i6<9>))
  • oa3ao322_x2 — width 10, drive 2.1, delay 1.2, q <= /((i0<10>.i1<9>.i2<9>) +((i3<9>+i4<9>+i5<9>).i6<9>))
  • oa3ao322_x4 — width 11, drive 4.3, delay 1.3, q <= /((i0<10>.i1<9>.i2<9>) +((i3<9>+i4<9>+i5<9>).i6<9>))
--------------------------------------------------------- AND/OR 8

💀 AND/OR 8

  • noa2a2a2a24_x1 — width 14, drive 0.6, delay 1.4, nq <= /((i0<14>.i1<14>)+(i2<13>.i3<13>) +(i4<13>.i5<13>)+(i6<14>.i7<14>))
  • noa2a2a2a24_x4 — width 17, drive 4.3, delay 1.7, nq <= /((i0<14>.i1<14>)+(i2<14>.i3<13>) +(i4<13>.i5<13>)+(i6<14>.i7<14>))
  • oa2a2a2a24_x2 — width 15, drive 2.1, delay 1.5, q <= ((i0<14>.i1<14>)+(i2<14>.i3<13>) +(i4<13>.i5<13>)+(i6<14>.i7<14>))
  • oa2a2a2a24_x4 — width 16, drive 4.3, delay 1.6, q <= ((i0<14>.i1<14>)+(i2<14>.i3<13>) +(i4<13>.i5<13>)+(i6<14>.i7<14>))
------------------------------------------------------ MULTIPLEXER

🔀 MULTIPLEXER

  • nmx2_x1 — width 7, drive 1.2, delay 1.0, nq <= /((i0<14>./cmd<21>)+(i1<14>.cmd))
  • nmx2_x4 — width 12, drive 4.3, delay 1.3, nq <= /((i0<8>./cmd<14>)+(i1<9>.cmd))
  • mx2_x2 — width 9, drive 2.1, delay 1.1, q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
  • mx2_x4 — width 10, drive 4.3, delay 1.3, q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
  • nmx3_x1 — width 12, drive 0.4, delay 1.2, nq <= /((i0<9>./cmd0<15>) +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
  • nmx3_x4 — width 15, drive 4.3, delay 1.7, nq <= /((i0<9>./cmd0<15>) +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
  • mx3_x2 — width 13, drive 2.1, delay 1.4, q <= ((i0<9>./cmd0<15>) +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
  • mx3_x4 — width 14, drive 4.3, delay 1.6, q <= ((i0<9>./cmd0<15>) +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
-------------------------------------------------------------- XOR

🔥 XOR

  • nxr2_x1 — width 9, drive 1.2, delay 1.1, nq <= /(i0<21>^i1<22>)
  • nxr2_x4 — width 11, drive 4.3, delay 1.2, nq <= /(i0<20>^i1<21>)
  • xr2_x1 — width 9, drive 1.2, delay 1.0, q <= (i0<21>^i1<22>)
  • xr2_x4 — width 12, drive 4.3, delay 1.2, q <= (i0<20>^i1<21>)
-------------------------------------------------------- FLIP-FLOP

👑 FLIP-FLOP

  • sff1_x4 — width 18, drive 4.3, delay 1.7, IF RISE(ck<8>). Two outputs here, bestie: nq <=/((i0<11>./cmd<13>)+(i1<7>.cmd)) and q <= i<8>
  • sff2_x4 — width 24, drive 4.3, delay 1.9, IF RISE(ck<8>), q <= ((i0<8>./cmd<16>)+(i1<7>.cmd))
  • sff3_x4 — width 28, drive 4.3, delay 2.4, IF RISE(ck<8>), q <= (i0<9>./cmd0<15>) +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0)
------------------------------------------------------------ ADDER

➕ ADDER

  • halfadder_x2 — width 16. Output sout: drive 2.1, delay 1.2, sout <= (a<27>^b<22>). Output cout: drive 2.1, delay 1.0, cout <= (a.b)
  • halfadder_x4 — width 18. Output sout: drive 4.3, delay 1.3, sout <= (a<27>^b<22>). Output cout: drive 4.3, delay 1.1, cout <= (a.b)
  • fulladder_x2 — width 20. Output sout: drive 2.1, delay 1.8, sout <= (a*<28>^b*<28>^cin*<19>). Output cout: drive 2.1, delay 1.4, cout <= (a*.b*+a*.cin*+b*.cin*)
  • fulladder_x4 — width 21. Output sout: drive 4.3, delay 2.2, sout <= (a*<28>^b*<28>^cin*<19>). Output cout: drive 4.3, delay 1.5, cout <= (a*.b*+a*.cin*+b*.cin*)
---------------------------------------------------------- SPECIAL

🫶 SPECIAL

  • zero_x0 — width 3, drive 0, delay 0, nq <= '0'
  • one_x0 — width 3, drive 0, delay 0, q <= '1'
  • tie_x0 — width 2, drive 0, delay 0, Body tie cell
  • rowend_x0 — width 1, drive 0, delay 0, Empty cell
=================================================================

🌈 NEW CELLS

Okay so the genuinely iconic part: you can add new cells to the library yourself. All it takes is dropping the 3 files — .ap, .al and .vbe — into the standard cell directory. That's it. That's the whole ritual. ✨

Here's the workflow, step by step:

  • The layout view can be created with the symbolic editor graal.
  • The physical outline is given above. 👆
  • The net-list view can be automatically generated with the lynx extractor.
  • The behavioral view has to be written by the designer (that's you 💅) and checked with the yagle functional abstractor.
Important: the file must contain the generic fields in order to be used by the logic synthesis tools, and the I/O terminals must be in the same order (alphabetic) in the .vbe and .al files. Don't skip that, it's giving chaos otherwise. 😭

And if you develop new cells — please, bestie, share the wealth — send the corresponding files to alliance-users@asim.lip6.fr 🫶

💾 VHDL FILES 💾

ok so bestie, sometimes you don't wanna read a table, you wanna read the actual VHDL. so here's the commented GENERIC for the na2_x4 cell, fr fr, straight from the source 💖

ENTITY na2_x4 IS
GENERIC (
  CONSTANT area          : NATURAL := 1750; -- lamba * lambda
  CONSTANT transistors   : NATURAL := 10;   -- number of
  CONSTANT cin_i0        : NATURAL := 10;   -- femto Farad for i0
  CONSTANT cin_i1        : NATURAL := 10;   -- femto Farad for i1
  CONSTANT tplh_i1_nq    : NATURAL := 606;  -- propag. time in pico-sec
                                            -- from i1 falling
                                            -- to   nq rizing
  CONSTANT rup_i1_nq     : NATURAL := 890;  -- resitance in Ohms when nq
                                            -- rizing due to i1 change
  CONSTANT tphl_i1_nq    : NATURAL := 349;  -- propag time when nq falls
  CONSTANT rdown_i1_nq   : NATURAL := 800;  -- resist when nq falls
  CONSTANT tplh_i0_nq    : NATURAL := 557;  -- idem for i0
  CONSTANT rup_i0_nq     : NATURAL := 890;
  CONSTANT tphl_i0_nq    : NATURAL := 408;
  CONSTANT rdown_i0_nq   : NATURAL := 800
);
PORT (
  i0     : in  BIT;
  i1     : in  BIT;
  nq     : out BIT;
  vdd    : in  BIT;
  vss    : in  BIT
);

like, look at her 💅 all the timing constants just sitting there in pico-seconds and Ohms, the area in lamba * lambda, the transistor count. it's giving fully documented cell. no cap, this is exactly the kind of thing you'd wanna peek at when you're debugging a delay you did not expect 😭

👀 SEE ALSO 👀

go read these too, they're the whole friend group 🫶

  • MBK_CATA_LIB (1)
  • catal (1)
  • ocp (1)
  • nero (1)
  • cougar (1)
  • boom (1)
  • loon (1)
  • boog (1)
  • genlib (1)
  • ap (5)
  • al (5)
  • vbe (5)

🐛 BUG REPORT 🐛

ok so real talk for a sec:

this tool is under development at the ASIM department of the LIP6 laboratory.

we need your feedback to improve documentation and tools. 💌

not me asking you to actually send feedback but like… bestie, please do 🙏 the docs and the tools both get better when people speak up, and that's on periodt.

and that's the whole page, you made it to the end 🎀 slay ✨ this one's from the ASIM/LIP6 girlies, dated October 19, 1999, filed under SXLIB(5) — mwah, go build something iconic 💖💅🦋

📦 where this page comes from