IICBUS(4)

πŸ’– iicbus β€” the I2C bus system, bestie πŸ’–

okay so. this is the iicbus manual page, from section 4 of the kernel interfaces manual, and we're gonna get through it together, no stress, no cap. πŸ¦‹


✨ SYNOPSIS ✨

like, here's the whole vibe in four lines:

device iicbus
device iicbb

device iic
device ic
device iicsmb

🌸 DESCRIPTION 🌸

The iicbus system gives you a uniform, modular, and architecture-independent setup for implementing drivers that control alllll the different I2C devices, and for making use of all the different I2C controllers. it's giving "one interface to rule them all" energy fr fr. πŸ‘‘


πŸ”Œ I2C πŸ”Œ

I2C is short for Inter Integrated Circuit bus. it was developed in the early 1980's by Philips semiconductors, and its whole purpose was to be an easy way to connect a CPU to peripheral chips inside a TV-set. iconic origin story tbh. πŸ“Ί

The BUS physically consists of 2 active wires plus a ground connection. The active wires β€” SDA and SCL β€” are both bidirectional. SDA is the Serial DAta line and SCL is the Serial CLock line. two wires, so much power. πŸ’…

Every component hooked up to the bus has its own unique address, whether it's a CPU, an LCD driver, a memory, or some complex function chip. Each of these chips can act as a receiver and/or a transmitter, depending on what it does. obviously an LCD driver is only a receiver, while a memory or I/O chip can be both transmitter and receiver. also, there may be one or more BUS MASTERs. 😀

The BUS MASTER is the chip that issues the commands on the BUS. in the I2C protocol specification it says that the IC which initiates a data transfer on the bus is considered the BUS MASTER, and at that moment all the others are regarded as the BUS SLAVEs. and like, as mentioned before, the IC bus is a Multi-MASTER BUS β€” meaning more than one IC capable of initiating data transfer can be connected to it. multiple main characters, we love to see it. πŸ‘‘


πŸŽ€ DEVICES πŸŽ€

Some I2C device drivers are available:

  • iic β€” general i/o operation
  • ic β€” network IP interface
  • iicsmb β€” I2C to SMB software bridge

🧚 INTERFACES 🧚

The I2C protocol may be implemented by hardware or by software. Software interfaces rely on very simple hardware β€” usually two lines twiddled by 2 registers. Hardware interfaces are more intelligent and receive 8-bit characters that they write to the bus according to the I2C protocol. ✨

I2C interfaces may act on the bus as slave devices, allowing spontaneous bidirectional communications, thanks to the multi-master capabilities of the I2C protocol. so generous of them. 🫢

Some I2C interfaces are available:

  • pcf β€” Philips PCF8584 master/slave interface
  • iicbb β€” generic bit-banging master-only driver
  • lpbb β€” parallel port specific bit-banging interface
  • bktr β€” Brooktree848 video chipset, hardware and software master-only interface

⚑ BUS FREQUENCY CONFIGURATION ⚑

The operating frequency of an I2C bus may be fixed or configurable. sometimes the bus is used as part of some larger standard interface, and that interface's specification may require a fixed frequency β€” in which case the driver for that hardware would not honor an attempt to configure a different speed. a general purpose I2C bus, like the ones found in many embedded systems, will often support multiple bus frequencies. πŸ’«

When a system supports multiple I2C buses, a different frequency can be configured for each bus by number, represented by the %d in the variable names below. Buses can be configured using any combination of device hints, Flattened Device Tree (FDT) data, tunables set via loader(8), or at runtime using sysctl(8). When configuration is supplied using more than one method, FDT and hint data will be overridden by a tunable, which can be overridden by sysctl(8). hierarchy!! the drama of it all. 😭

🌈 Device Hints 🌈

Set hint.iicbus.%d.frequency to the frequency in Hz, on systems that use device hints to configure I2C devices. The hint is also honored by systems that use FDT data if no frequency is configured using FDT.

🌸 Flattened Device Tree Data 🌸

Configure the I2C bus speed using the FDT standard clock-frequency property of the node describing the I2C controller hardware.

πŸ’… Sysctl and Tunable πŸ’…

Set dev.iicbus.%d.frequency in loader.conf(5). The same variable can be changed at any time with sysctl(8). Reset the bus using i2c(8) or the iic(4) I2CRSTCARD ioctl to make the change take effect.

not me stressing that you literally have to reset the bus for it to actually do anything. do NOT skip that step bestie, i'm begging. πŸ™ˆ

πŸ‘€ SEE ALSO πŸ‘€


πŸ“œ HISTORY πŸ“œ

The iicbus manual page first appeared in FreeBSD 3.0. a true elder. ⭐


πŸ’– AUTHORS πŸ’–

This manual page was written by Nicolas Souchu. thank you king 🫢


and that's the whole page!! this one came from the Debian crew, dated January 15, 2017, and it's filed under IICBUS(4) β€” ily, go configure a bus, slay πŸ’…βœ¨

πŸ“¦ where this page comes from