CXGBE(4)
β¨ NAME β¨
okay so bestie, cxgbe(4) is literally the Chelsio T7, T6, T5, and T4 based 1Gb to 400Gb Ethernet driver. iconic π
π οΈ SYNOPSIS π οΈ
You wanna compile this driver into the kernel? slay, just put these lines in your kernel configuration file:
device cxgbe
Or you wanna load the driver as a module at boot time? say less, put these lines in loader.conf(5):
t7fw_cfg_load="YES"
t6fw_cfg_load="YES"
t5fw_cfg_load="YES"
t4fw_cfg_load="YES"
if_cxgbe_load="YES"
π DESCRIPTION π
The cxgbe driver provides support for PCI Express Ethernet adapters based on the Chelsio Terminator 7, Terminator 6, Terminator 5, and Terminator 4 ASICs (T7, T6, T5, and T4). main character energy fr fr π¦
It supports Jumbo Frames, Transmit/Receive checksum offload, TCP segmentation offload (TSO), Large Receive Offload (LRO), VLAN tag insertion/extraction, VLAN checksum offload, VLAN TSO, VXLAN checksum offload, VXLAN TSO, and Receive Side Steering (RSS). For further hardware information and questions related to hardware requirements, see http://www.chelsio.com/.
The cxgbe driver uses different names for devices based on the associated ASIC. vibe check π
- T7 β Port Name:
che; Parent Device:chnex; Virtual Interface:vche. - T6 β Port Name:
cc; Parent Device:t6nex; Virtual Interface:vcc. - T5 β Port Name:
cxl; Parent Device:t5nex; Virtual Interface:vcxl. - T4 β Port Name:
cxgbe; Parent Device:t4nex; Virtual Interface:vcxgbe.
Loader tunables with the hw.cxgbe prefix apply to all cards. The driver provides sysctl MIBs for both ports and parent devices using the names above. For example, a T5 adapter provides port MIBs under dev.cxl and adapter-wide MIBs under dev.t5nex. References to sysctl MIBs in the remainder of this page use dev.<port> for port MIBs and dev.<nexus> for adapter-wide MIBs.
For more information on configuring this device, see ifconfig(8). periodt π
π¦ HARDWARE π¦
not me listing every single model, but yes bestie, all of them are here πΈ
β¨ T7 ASIC β¨
The cxgbe driver supports 400Gb, 200Gb, 50Gb, and 10Gb Ethernet adapters based on the T7 ASIC:
- Chelsio S71400
- Chelsio S72200
- Chelsio S72200-OCP
- Chelsio T72200
- Chelsio T72200-DPU
- Chelsio T72200-FH
- Chelsio T72200-FH-DPU
- Chelsio T72200-OCP
- Chelsio S7450-DPU
- Chelsio S7450-OCP
- Chelsio T71200-iNIC
- Chelsio T7250
- Chelsio T7210-BT
- Chelsio T7410-BT-OCP
π T6 ASIC π
The cxgbe driver supports 100Gb and 25Gb Ethernet adapters based on the T6 ASIC:
- Chelsio T6225-CR
- Chelsio T6225-SO-CR
- Chelsio T62100-LP-CR
- Chelsio T62100-SO-CR
- Chelsio T62100-CR
π©΅ T5 ASIC π©΅
The cxgbe driver supports 40Gb, 10Gb and 1Gb Ethernet adapters based on the T5 ASIC:
- Chelsio T580-CR
- Chelsio T580-LP-CR
- Chelsio T580-LP-SO-CR
- Chelsio T560-CR
- Chelsio T540-CR
- Chelsio T540-LP-CR
- Chelsio T522-CR
- Chelsio T520-LL-CR
- Chelsio T520-CR
- Chelsio T520-SO
- Chelsio T520-BT
- Chelsio T504-BT
π T4 ASIC π
The cxgbe driver supports 10Gb and 1Gb Ethernet adapters based on the T4 ASIC:
- Chelsio T420-CR
- Chelsio T422-CR
- Chelsio T440-CR
- Chelsio T420-BCH
- Chelsio T440-BCH
- Chelsio T440-CH
- Chelsio T420-SO
- Chelsio T420-CX
- Chelsio T420-BT
- Chelsio T404-BT
π LOADER TUNABLES π
Tunables can be set at the loader(8) prompt before booting the kernel or stored in loader.conf(5). There are multiple tunables that control the number of queues of various types. A negative value for such a tunable instructs the driver to create up to that many queues if there are enough CPU cores available. iykyk π§
hw.cxgbe.ntxqβ Number of NIC tx queues used for a port. The default is 16 or the number of CPU cores in the system, whichever is less.hw.cxgbe.nrxqβ Number of NIC rx queues used for a port. The default is 8 or the number of CPU cores in the system, whichever is less.hw.cxgbe.nofldtxqβ Number of TOE tx queues used for a port. The default is 8 or the number of CPU cores in the system, whichever is less.hw.cxgbe.nofldrxqβ Number of TOE rx queues used for a port. The default is 2 or the number of CPU cores in the system, whichever is less.hw.cxgbe.num_visβ Number of virtual interfaces (VIs) created for each port. Each virtual interface creates a separate network interface. The first virtual interface on each port is required and represents the primary network interface on the port. Additional virtual interfaces on a port are named using the Virtual Interface name from the table above. Additional virtual interfaces use a single pair of queues for rx and tx as well as an additional pair of queues for TOE rx and tx. The default is 1.hw.cxgbe.holdoff_timer_idx,hw.cxgbe.holdoff_timer_idx_ofldβ Timer index value used to delay interrupts. The holdoff timer list has the values 1, 5, 10, 50, 100, and 200 by default (all values are in microseconds) and the index selects a value from this list.holdoff_timer_idx_ofldapplies to queues used for TOE rx. The default value is 1 which means the timer value is5us. Different interfaces can be assigned different values at any time via thedev.<port>.X.holdoff_tmr_idxanddev.<port>.X.holdoff_tmr_idx_ofldsysctls.hw.cxgbe.holdoff_pktc_idx,hw.cxgbe.holdoff_pktc_idx_ofldβ Packet-count index value used to delay interrupts. The packet-count list has the values 1, 8, 16, and 32 by default, and the index selects a value from this list.holdoff_pktc_idx_ofldapplies to queues used for TOE rx. The default value is -1 which means packet counting is disabled and interrupts are generated based solely on the holdoff timer value. Different interfaces can be assigned different values via thedev.<port>.X.holdoff_pktc_idxanddev.<port>.X.holdoff_pktc_idx_ofldsysctls.
lowkey important: these sysctls work only when the interface has never been marked up (as done by ifconfig up). π«Ά
hw.cxgbe.qsize_txqβ Number of entries in a transmit queue's descriptor ring. Abuf_ringof the same size is also allocated for additional software queuing. Seeifnet(9). The default value is 1024. Different interfaces can be assigned different values via thedev.<port>.X.qsize_txqsysctl.
same vibe check as before: this sysctl works only when the interface has never been marked up (as done by ifconfig up). π
hw.cxgbe.qsize_rxqβ Number of entries in a receive queue's descriptor ring. The default value is 1024. Different interfaces can be assigned different values via thedev.<port>.X.qsize_rxqsysctl.
and again bestie: this sysctl works only when the interface has never been marked up (as done by ifconfig up). π
hw.cxgbe.interrupt_typesβ Permitted interrupt types. Bit 0 represents INTx (line interrupts), bit 1 MSI, and bit 2 MSI-X. The default is 7 (all allowed). The driver selects the best possible type out of the allowed types.hw.cxgbe.pcie_relaxed_orderingβ PCIe Relaxed Ordering. -1 indicates the driver should determine whether to enable or disable PCIe RO. 0 disables PCIe RO. 1 enables PCIe RO. 2 indicates the driver should not modify the PCIe RO setting. The default is -1.hw.cxgbe.fw_installβ 0 prohibits the driver from installing a firmware on the card. 1 allows the driver to install a new firmware if internal driver heuristics indicate that the new firmware is preferable to the one already on the card. 2 instructs the driver to always install the new firmware on the card as long as it is compatible with the driver and is a different version than the one already on the card. The default is 1.hw.cxgbe.fl_pktshiftβ Number of padding bytes inserted before the beginning of an Ethernet frame in the receive buffer. The default value is 0. A value of 2 would ensure that the Ethernet payload (usually the IP header) is at a 4 byte aligned address. 0-7 are all valid values.hw.cxgbe.fl_padβ A non-zero value ensures that writes from the hardware to a receive buffer are padded up to the specified boundary. The default is -1 which lets the driver pick a pad boundary. 0 disables trailer padding completely.hw.cxgbe.cong_dropβ Controls the hardware response to congestion. -1 disables congestion feedback and is not recommended.
fr fr, do not sleep on that βnot recommendedβ β that's a real warning. β οΈ
- 0 instructs the hardware to backpressure its pipeline on congestion. This usually results in the port emitting PAUSE frames.
- 1 instructs the hardware to drop frames destined for congested queues.
- 2 instructs the hardware to both backpressure the pipeline and drop frames.
hw.cxgbe.pause_settingsβ PAUSE frame settings. Bit 0 isrx_pause, bit 1 istx_pause, bit 2 ispause_autoneg.rx_pause = 1instructs the hardware to heed incoming PAUSE frames, 0 instructs it to ignore them.tx_pause = 1allows the hardware to emit PAUSE frames when its receive FIFO reaches a high threshold, 0 prohibits the hardware from emitting PAUSE frames.pause_autoneg = 1overrides therx_pauseandtx_pausebits and instructs the hardware to negotiate PAUSE settings with the link peer. The default is 7 (all three = 1). This tunable establishes the default PAUSE settings for all ports. Settings can be displayed and controlled on a per-port basis via thedev.<port>.X.pause_settingssysctl.hw.cxgbe.fecβ Forward Error Correction settings. -1 (default) means driver should automatically pick a value. 0 disables FEC. Finer grained control can be achieved by setting individual bits. Bit 0 enables RS FEC, bit 1 enables BASE-R FEC (aka Firecode FEC), bit 2 enables NO FEC, and bit 6 enables the FEC that is recommended by the transceiver/cable that is plugged in. These bits can be set together in any combination. This tunable establishes the default FEC settings for all ports. Settings can be controlled on a per-port basis via thedev.<port>.X.requested_fecsysctl. The FEC in use on the link is available indev.<port>.X.link_fecwhen the link is up.hw.cxgbe.autonegβ the link autonegotiation settings, bestie π . This tunable sets up the default autoneg behaviour for all ports at once, but you can peek at and control it per-port via thedev.<port>.X.autonegsysctl.0disables autonegotiation,1enables it, and the default is-1which just lets the driver pick a value for you (main character energy tbh). Oh and heads up:dev.<port>.X.autonegis-1for port + module combos that straight up don't support autonegotiation β not a bug, just how it is π«Άhw.cxgbe.buffer_packingβ lets the hardware deliver multiple frames in the same receive buffer opportunistically β¨. Default is-1which means the driver decides (trust her judgment honestly), and0or1explicitly disable or enable the feature. No in-between vibes.hw.cxgbe.largest_rx_clusterhw.cxgbe.safest_rx_cluster
Ok so these two are the sizes of rx clusters and they're a package deal, so listen up π£. Each one has to be set to one of the sizes available (usually 2048, 4096, 9216, and 16384), and largest_rx_cluster must be greater than or equal to safest_rx_cluster β the driver is not gonna let you set up a cursed inverted pair, no ma'am. The defaults are 16384 and 4096 respectively. Here's the tea: the driver never attempts to allocate a receive buffer larger than largest_rx_cluster, and it falls back to allocating buffers of safest_rx_cluster size if an allocation larger than safest_rx_cluster fails π. Also important β largest_rx_cluster merely establishes a ceiling. The driver is fully allowed to allocate buffers of smaller sizes. It's giving "maximum, not requirement" π
hw.cxgbe.config_fileβ picks a pre-packaged device configuration file π. A configuration file contains a recipe for partitioning and configuring the hardware resources on the card. This tunable is for specialized applications only and should not be used in normal operation β like, genuinely, don't. The configuration profile currently in use is available in thedev.<nexus>.X.cfanddev.<nexus>.X.cfcsumsysctls if you wanna see what you're working with πhw.cxgbe.linkcaps_allowedhw.cxgbe.niccaps_allowedhw.cxgbe.toecaps_allowedhw.cxgbe.rdmacaps_allowedhw.cxgbe.iscsicaps_allowedhw.cxgbe.fcoecaps_allowed
These six are the capability toggles and they all work the same way, so I'm grouping them πΈ. Disallowing a capability provides a hint to the driver and firmware to not reserve hardware resources for that feature. Each of these is a bit field with a bit for each sub-capability within the capability (yes, we're going nested, it's that kind of party). Like config_file up there, this tunable is for specialized applications only and should not be used in normal operation π«. The capabilities for which hardware resources have been reserved are listed in the dev.<nexus>.X.*caps sysctls β that's your vibe check.
hw.cxgbe.tx_vm_wrβ setting this to1instructs the driver to use VM work requests to transmit data π₯. This lets PF interfaces transmit frames to VF interfaces over the internal switch in the ASIC. Quick note bestie: thecxgbev(4)VF driver always uses VM work requests and is not affected by this tunable at all β she lives her truth. The default value is0and should be changed only if PF and VF interfaces need to communicate with each other. Different interfaces can be assigned different values using thedev.<port>.X.tx_vm_wrsysctl when the interface is administratively down π«‘hw.cxgbe.attack_filterβ set to1to enable the "attack filter" π‘οΈ. Default is0. The attack filter will drop an incoming frame if any of these conditions is true:- src ip/ip6 == dst ip/ip6
- tcp and src/dst ip is not unicast
- src/dst ip is loopback (
127.x.y.z) - src ip6 is not unicast
- src/dst ip6 is loopback (
::1/128) or unspecified (::/128) - tcp and src/dst ip6 is mcast (
ff00::/8)
This facility is available on T4 and T5 based cards only β older girlies don't get the perk, sorry π
hw.cxgbe.drop_ip_fragmentsβ set to1to drop all incoming IP fragments. Default is0. Warning though: this drops valid frames too, so like... know what you're doing πhw.cxgbe.drop_pkts_with_l2_errorsβ set to1to drop incoming frames with Layer 2 length or checksum errors. Default is1β yes queen, filtering is on by default πhw.cxgbe.drop_pkts_with_l3_errorsβ set to1to drop incoming frames with IP version, length, or checksum errors. The IP checksum is validated for TCP or UDP packets only, fyi. Default is0πΈhw.cxgbe.drop_pkts_with_l4_errorsβ set to1to drop incoming frames with Layer 4 (TCP or UDP) length, checksum, or other errors. Default is0β¨
π SUPPORT π
For general information and support, go to the Chelsio support website at: http://www.chelsio.com/ π
If an issue is identified with this driver with a supported adapter, email all the specific information related to the issue to β¨support@chelsio.comβ© π§. Like, all of it β don't make them guess, bestie.
π¦ SEE ALSO π¦
arp(4), ccr(4), cxgb(4), cxgbev(4), netintro(4), ng_ether(4), ifconfig(8)
Go read the friends, they're all linked in this little universe iykyk π
π HISTORY π
The cxgbe device driver first appeared in FreeBSD 9.0 π. Support for T5 cards first appeared in FreeBSD 9.2 and FreeBSD 10.0. Support for T6 cards first appeared in FreeBSD 11.1 and FreeBSD 12.0. Support for T7 cards first appeared in FreeBSD 15.0 π. A whole glow-up timeline, honestly.
π AUTHORS π
The cxgbe driver was written by Navdeep Parhar β¨np@FreeBSD.orgβ© π«Ά. Iconic. Legendary. We stan.
And that's the whole page, bestie β this Debian build of CXGBE(4) is dated December 17, 2025, so go forth and configure your Chelsio card responsibly πβ¨π
π¦ where this page comes from
- freebsd 15.1: base 15.1
- Copyright (c) 2011-2016, Chelsio Inc
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms