OPENSSL_RISCVCAP(3SSL)

💖 OPENSSL_RISCVCAP 💖

okay bestie, welcome to OPENSSL_riscvcap(3SSL), aka the page in the OpenSSL manual all about the RISC-V processor capabilities vector. no cap, it's shorter than it looks. let's go 🦋

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✨ NAME ✨

OPENSSL_riscvcap — the RISC-V processor capabilities vector 🌈

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✨ SYNOPSIS ✨

env OPENSSL_riscvcap=... <application>

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✨ DESCRIPTION ✨

so like, libcrypto supports RISC-V instruction set extensions, periodt. each one of those extensions gets its own little name in the capabilities vector 👑

on Linux, when libcrypto initializes, whatever the RISC-V Hardware Probing syscall (hwprobe) hands back gets stored in the vector. on anything else? every single capability is disabled. it's giving nothing. 💀

but bestie, you can override the set of instructions an application gets to see — just set the OPENSSL_riscvcap environment variable before you start the application 🫶

this env var is lowkey similar to the RISC-V ISA string from the RISC-V Instruction Set Manual, and it's case insensitive (iconic of it). BUT — because the environment variable parser inside libcrypto has limits, an extension has to be prefixed with an underscore to be recognizable. yes, this applies to the Vector extension too 🙈

 OPENSSL_riscvcap="rv64gc_v_zba_zbb_zbs..."

⚠️ heads up: extension implication is currently not implemented. so if you pass "rv64gc_b" as the environment variable, zba/zbb/zbs would not get implied in the capability vector. no freebies, fr fr.

currently only these extensions are recognized 👇

• ZBA — Address Generation
  • Could be detected using hwprobe for Linux kernel >= 6.5
• ZBB — Basic bit-manipulation
  • Could be detected using hwprobe for Linux kernel >= 6.5
• ZBC — Carry-less multiplication
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZBS — Single-bit instructions
  • Could be detected using hwprobe for Linux kernel >= 6.5
• ZBKB — Bit-manipulation for Cryptography
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZBKC — Carry-less multiplication for Cryptography
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZBKX — Crossbar permutations
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZKND — NIST Suite: AES Decryption
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZKNE — NIST Suite: AES Encryption
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZKNH — NIST Suite: Hash Function Instructions
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZKSED — ShangMi Suite: SM4 Block Cipher Instructions
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZKSH — ShangMi Suite: SM3 Hash Function Instructions
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZKR — Entropy Source Extension
• ZKT — Data Independent Execution Latency
  • Could be detected using hwprobe for Linux kernel >= 6.8
• V — Vector Extension for Application Processors
  • Could be detected using hwprobe for Linux kernel >= 6.5
• ZVBB — Vector Basic Bit-manipulation
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZVBC — Vector Carryless Multiplication
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZVKB — Vector Cryptography Bit-manipulation
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZVKG — Vector GCM/GMAC
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZVKNED — NIST Suite: Vector AES Block Cipher
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZVKNHA — NIST Suite: Vector SHA-2 Secure Hash
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZVKNHB — NIST Suite: Vector SHA-2 Secure Hash
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZVKSED — ShangMi Suite: SM4 Block Cipher
  • Could be detected using hwprobe for Linux kernel >= 6.8
• ZVKSH — ShangMi Suite: SM3 Secure Hash
  • Could be detected using hwprobe for Linux kernel >= 6.8

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✨ RETURN VALUES ✨

Not available. that's it, that's the section 😭

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✨ EXAMPLES ✨

okay so first, checking what capabilities are currently detected 🔍

$ openssl info -cpusettings
OPENSSL_riscvcap=RV64GC_ZBA_ZBB_ZBC_ZBS_V vlen:256

📝 note: the first word in the displayed capabilities is the RISC-V base architecture value, and it's derived from the compiler configuration — which means it is not overridable by the environment variable, bestie. and when the V extension is given, the riscv_vlen value is always displayed; there is no way to override the riscv_vlen by the environment variable either. it is what it is 💅

disables all instruction set extensions (going full minimalist, we love a clean slate) 🎀

export OPENSSL_riscvcap="rv64gc"

only enable the vector extension (main character energy only) ⭐

export OPENSSL_riscvcap="rv64gc_v"

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✨ COPYRIGHT ✨

Copyright 2024 The OpenSSL Project Authors. All Rights Reserved.

Licensed under the Apache License 2.0 (the "License"). You may not use this file except in compliance with the License. You can obtain a copy in the file LICENSE in the source distribution or at <https://www.openssl.org/source/license.html>.

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that's the whole page babes 🫶 this was version 4.0.3, dated 2026-09-29, and yes it's giving OpenSSL energy the entire time. go forth and configure ur RISC-V extensions, u absolute icon 👑💖✨