rte_prefetch.h(3)
β¨ rte_prefetch.h β¨
okay bestie, welcome to the rte_prefetch.h manual page, third section of the manual, and it's giving speed. this is the DPDK header that teaches your CPU to grab data before it's even asked for it. main character energy fr fr π
π SYNOPSIS π
#include <rte_compat.h>
πΈ Functions πΈ
static void rte_prefetch0 (const volatile void *p)
static void rte_prefetch1 (const volatile void *p)
static void rte_prefetch2 (const volatile void *p)
static void rte_prefetch_non_temporal (const volatile void *p)
static __rte_experimental void rte_prefetch0_write (const void *p)
static __rte_experimental void rte_prefetch1_write (const void *p)
static __rte_experimental void rte_prefetch2_write (const void *p)
static __rte_experimental void rte_cldemote (const volatile void *p)
π Detailed Description π
Prefetch operations. that's the whole vibe. β¨
ngl this file defines an API for prefetch macros / inline-functions, and bestie, they are architecture-dependent. what does prefetching even mean? it's when a processor requests an instruction or data from memory to cache before it is actually needed, potentially speeding up the execution of the program. it's the CPU equivalent of ordering your boba before you even get to the shop. iconic. π§
Definition in file rte_prefetch.h.
π Function Documentation π
π¦ void rte_prefetch0 (const volatile void * p) [inline], [static] π¦
Prefetch a cache line into all cache levels. every single one. no crumbs left.
Parameters
pβ Address to prefetch
π¦ void rte_prefetch1 (const volatile void * p) [inline], [static] π¦
Prefetch a cache line into all cache levels except the 0th cache level. like, we're skipping one, and it's the first one, and that's a choice but it's the documented one. π
Parameters
pβ Address to prefetch
π¦ void rte_prefetch2 (const volatile void * p) [inline], [static] π¦
Prefetch a cache line into all cache levels except the 0th and 1th cache levels. yes bestie, the original says "1th" and I am not correcting it, that's load-bearing lore. π
Parameters
pβ Address to prefetch
π¦ void rte_prefetch_non_temporal (const volatile void * p) [inline], [static] π¦
Prefetch a cache line into all cache levels, but make it non-temporal/transient β¨
so here's the tea: the non-temporal prefetch is intended as a prefetch hint that the processor will use the prefetched data only once or for a short period β unlike the rte_prefetch0() function, which implies that the prefetched data is going to be used repeatedly. one-time hangout vs. situationship. you get it.
Parameters
pβ Address to prefetch
π₯ __rte_experimental void rte_prefetch0_write (const void * p) [inline], [static] π₯
Warning π¨ EXPERIMENTAL: this API may change, or be removed, without prior notice
Prefetch a cache line into all cache levels, with intention to write. this prefetch variant hints to the CPU that the program is expecting to write to the cache line being prefetched. telling the CPU your plans ahead of time? communication, we love to see it. π«Ά
Parameters
pβ Address to prefetch
Definition at line 72 of file rte_prefetch.h.
π₯ __rte_experimental void rte_prefetch1_write (const void * p) [inline], [static] π₯
Warning π¨ EXPERIMENTAL: this API may change, or be removed, without prior notice
Prefetch a cache line into all cache levels, except the 0th, with intention to write. this prefetch variant hints to the CPU that the program is expecting to write to the cache line being prefetched. same energy, one less cache level. β
Parameters
pβ Address to prefetch
Definition at line 97 of file rte_prefetch.h.
π₯ __rte_experimental void rte_prefetch2_write (const void * p) [inline], [static] π₯
Warning π¨ EXPERIMENTAL: this API may change, or be removed, without prior notice
Prefetch a cache line into all cache levels, except the 0th and 1st, with intention to write. this prefetch variant hints to the CPU that the program is expecting to write to the cache line being prefetched. (yes, "1st" this time, no "1th", the source said "1st" here β we report, we don't editorialize π)
Parameters
pβ Address to prefetch
Definition at line 122 of file rte_prefetch.h.
π __rte_experimental void rte_cldemote (const volatile void * p) [inline], [static] π
Warning π¨ EXPERIMENTAL: this API may change, or be removed, without prior notice
Demote a cache line to a more distant level of cache from the processor.
CLDEMOTE hints to hardware to move (demote) a cache line from the closest to the processor to a level more distant from the processor. and before you come for me: it is a hint and not guaranteed. rte_cldemote is intended to move the cache line to the more remote cache, where it expects sharing to be efficient and to indicate that a line may be accessed by a different core in the future. it's the "you're not my problem anymore, but like, in a collaborative way" of cache lines. π¦
Parameters
pβ Address to demote
π Author π
Generated automatically by Doxygen for DPDK from the source code. not a human, just a very diligent little script doing its thing. π€π
and that's the whole page, bestie β stay hydrated, stay cache-hot, and may your prefetches always land. bye babes π β¨
DPDK, Version 25.11.3 β that's the source and version of this rte_prefetch.h(3) page right there. mwah. π
π¦ where this page comes from
- ubuntu resolute: dpdk-doc 25.11.3-0ubuntu0.26.04.1 Β· BSD-3-Clause
- ubuntu stonking: dpdk-doc 25.11.3-1 Β· BSD-3-Clause
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash on : a language model's rewrite of the original, under its terms