LIBPFM(3)

💖 LIBPFM(3) — bestie edition 💖

okay so this is from the Linux Programmer's Manual, section 3, and we're about to become so unwell about Intel SapphireRapids performance monitoring. grab a strawberry drink 🍓, we're going in.

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✨ NAME ✨

libpfm_intel_spr — it's giving support for Intel SapphireRapids core PMU. that's the whole name, no notes 💅

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🌸 SYNOPSIS 🌸

#include <perfmon/pfmlib.h>

• PMU name: spr
• PMU desc: Intel SapphireRapids

like. that's it. that's the entry point. short and iconic fr fr.

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🦋 DESCRIPTION 🦋

so the library supports the Intel SapphireRapids core PMU. but bestie, listen, real talk: this PMU model only covers each core's PMU, not the socket level PMU. core girlies only, socket girlies can go elsewhere 🙈

on SapphireRapids, the number of generic counters depends on the Hyperthreading (HT) mode. so it literally vibes differently depending on whether HT is on or off.

and the pfm_get_pmu_info() function returns the maximum number of generic counters in num_cntrs. that's your number, that's what you get ✨

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💅 MODIFIERS 💅

here's the whole roster of modifiers supported on Intel SapphireRapids processors. every single one, no skipping, we don't do that here 👑

• u — measure at user level, which includes privilege levels 1, 2, 3. this corresponds to PFM_PLM3. it's a boolean modifier. ✨
• k — measure at kernel level, which includes privilege level 0. this corresponds to PFM_PLM0. also a boolean modifier. 🌸
• i — invert the meaning of the event. the counter will now count cycles in which the event is not occurring. boolean modifier. it's giving reverse uno 🃏
• e — enable edge detection, i.e., count only when there's a state transition from no occurrence of the event to at least one occurrence. ⚠️ this modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. boolean modifier. do not skip the buddy system on this one bestie.
• c — set the counter mask value. the mask acts as a threshold: the counter will count the number of cycles in which the number of occurrences of the event is greater or equal to the threshold. this is an integer modifier with values in the range [0:255]. 🎀
• ldlat — pass a latency threshold to the MEM_TRANS_RETIRED:LOAD_LATENCY event. this is an integer attribute that must be in the range [1:65535]. it is required for this event. 📌 note that the event must be used with precise sampling (PEBS). yes it's required-required, not optional-required.
• intx — monitor the event only when executing inside a transactional memory region (in tx). the event does not count otherwise. this is a boolean modifier, plural typo and all, we love her. default value is 0. 🌈
• intxcp — do not count occurrences of the event when they are inside an aborted transactional memory region. boolean modifier. default value is 0. 🫶
• fe_thres — this modifier is for the FRONTEND_RETIRED event only. it defines the period in core cycles after which the IDQ_*_BUBBLES umask counts. it acts as a threshold, i.e., at least a period of N core cycles where the frontend did not deliver X uops. it can only be used with the IDQ_*_BUBBLES umasks. if not specified, the default threshold value is 1 cycle. the valid values are in [1-4095]. 🔥

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👑 OFFCORE_RESPONSE events 👑

Intel SapphireRapids supports two encodings for offcore_response events. in the library, these are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. two of them. twins, basically 💜

those events need special treatment in the performance monitoring infrastructure because each event uses an extra register to store some settings. so in case multiple offcore_response events are monitored simultaneously, the operating system needs to manage the sharing of that extra register. sharing is caring but also sharing is a whole OS responsibility, not yours 🧚

the offcore_response events are exposed as normal events by the library. the extra settings are exposed as regular umasks. the library takes care of encoding the events according to the underlying kernel interface. you just vibe, she handles the encoding ✨

on Intel SapphireRapids, unlike older processors, the event is treated as a regular event with a flat set of umasks to choose from. it is not possible to combine the various requests, supplier, snoop bits anymore. so sorry to the combine-everything girlies 😭 therefore the library offers the list of validated combinations as per Intel's official event list. validated only. periodt.

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🌈 Topdown via PERF_METRICS 🌈

Intel SapphireRapids supports the PERF_METRICS MSR which provides support for Topdown Level 1 and 2 via a single PMU counter. this special counter provides percentages of slots for each metric.

⚠️ this feature must be used in conjunction with fixed counter 3, which counts SLOTS, in order to work properly.

the Linux kernel exposes PERF_METRICS metrics as individual pseudo events counting in slots unit — however, to operate correctly, all events must be programmed together. the Linux kernel requires all PERF_METRICS events to be programmed as a single event group with the first event as SLOTS required. example:

'{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}'

libpfm4 provides access to the PERF_METRICS pseudo events via a dedicated event called TOPDOWN_M. this event uses the pseudo encodings assigned by the Linux kernel to PERF_METRICS pseudo events. using these encodings ensures the kernel detects them as targeting the PERF_METRICS MSR. 📌 note that libpfm4 only provides the encodings, and that it is up to the user on Linux to group them and order them properly for the perf_events interface.

there exists generic counter encodings for most of the Topdown metrics and libpfm4 provides support for those via the TOPDOWN event. note that all subevents of TOPDOWN_M use fixed counters, which have, by definition, no actual event codes. the library uses the Linux pseudo event codes for them, even when compiled on non-Linux operating systems. the same holds true for any fixed counters pseudo event exported by libpfm4. cross-platform consistency queen 💅

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🎀 AUTHORS 🎀

Stephane Eranian <eranian@gmail.com> — thank you for your service, legend 🫶

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one (1) author. one (1) email address. we love a solo main character moment.

and that's the whole page bestie, no cap, every flag and every caveat intact, iykyk 💖

LIBPFM(3) — April, 2022 — that's the version and date, stamped and slayed. bye bestie, go count some counters 🌸✨